Digital ASIC Design Engineer for Mixed-Signal IPs

Job Title

Digital ASIC Design Engineer for Mixed-Signal IPs

Role Summary

Design digital RTL and ASIC implementation for mixed-signal IP blocks (DAC, ADC, PLL and similar) to be integrated into SoCs. Work as part of a cross-functional team including system architects, analog designers, verification and physical design engineers.

Deliver micro-architecture, RTL, and support implementation through timing closure and silicon bring-up to meet power, performance, and area targets.

Experience Level

Mid-level — typically 3+ years of relevant RTL and ASIC design experience (posting lists ranges from 2+ to 8+ years across qualifications).

Responsibilities

Core responsibilities include:

• Architect and define the digital portions of mixed-signal IPs in collaboration with system and analog teams.
• Develop micro-architecture and implement RTL for complex mixed-signal IP blocks.
• Optimize designs for power, performance, and area.
• Use front-end ASIC tools for lint, CDC, DFT, synthesis, formal verification, and static timing analysis.
• Design and analyze DFT logic and support ATPG for SAF/TDF coverage.
• Create hardware specifications and comprehensive design documentation.
• Collaborate with DV and PD teams to verify designs, support floorplanning/placement, and achieve timing closure.
• Support SoC integration, pre-silicon verification, and post-silicon bring-up and debug.

Requirements

Must-have technical skills and experience (minimum necessary):

• 3+ years of hands-on RTL and ASIC digital design experience (RTL development through tape-out flow).
• Proficiency with industry front-end and implementation tools such as VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler, and Spyglass.
• Experience with CDC analysis, synthesis, STA, formal verification, and DFT methodologies.
• Ability to develop and deliver RTL micro-architectures and work closely with verification and physical design teams.
• Strong debugging skills for pre-silicon simulation and post-silicon bring-up.

Nice-to-have:

• Experience implementing mixed-signal-related IPs (SerDes, DDR PHY, PLLs, DACs, ADCs, sensors) in ASIC flows.
• Background in low-power digital design techniques and high-speed digital circuit design.
• Experience developing automation and productivity scripts/tools using Python or Perl.

Education Requirements

The posting references graduate and undergraduate degrees: Master's degree in Electrical Engineering, Computer Engineering, or a related field is listed under required qualifications for the role. Minimum qualifications also permit a Bachelor's degree in Science/Engineering (with 2+ years relevant experience), a Master's degree (with 1+ year), or a PhD. Fields mentioned include Electrical Engineering and Computer Engineering; equivalent practical experience is accepted per the minimum-qualifications language.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.