Digital ASIC Design Engineer for Mixed-Signal IPs

Job Title

Digital ASIC Design Engineer for Mixed-Signal IPs

Role Summary

Design and implement digital logic and RTL for mixed-signal IP blocks (DAC, ADC, PLL and similar) for integration into Qualcomm SoCs. Work on micro-architecture, front-end RTL implementation, verification handoff and support for physical integration and silicon bring-up.

Collaborate with system architects, analog designers, verification and physical-design teams to achieve power, performance, area and testability targets.

Experience Level

Mid-level — typically 3+ years of professional RTL and ASIC design experience per the posting.

Responsibilities

Deliver RTL and support the full ASIC front-end and integration flow for mixed-signal IPs.

• Architect digital micro-architecture and implement RTL for mixed-signal IPs in coordination with system and analog teams.
• Optimize designs for power, performance and area using digital-architecture and DSP techniques.
• Use industry-standard flows and tools for lint, CDC analysis, DFT, synthesis, formal verification and static timing analysis.
• Design and analyze DFT logic including ATPG for stuck-at and transition-delay fault coverage.
• Produce hardware specifications and design documentation.
• Collaborate with DV teams to define test plans, debug functional issues and close verification gaps.
• Coordinate with physical-design teams to support floorplanning, placement and timing closure.
• Support SoC integration, pre-silicon simulation and post-silicon bring-up/debug.

Requirements

Core technical skills and experience required or strongly preferred. Degree requirements are summarized under Education Requirements below.

Must-have

• 3+ years of RTL and ASIC design experience focused on front-end design and implementation.
• Proficiency with front-end and implementation tools such as VCS, Fusion Compiler, PrimeTime, Power Compiler (PTPX), DFT Compiler and Spyglass.
• Experience with micro-architecture, RTL coding, CDC, lint, DFT, synthesis, formal verification and STA flows.
• Experience working with verification (DV) and physical-design (PD) teams and supporting SoC integration/debug.

Nice-to-have

• 5+ years of experience in high-speed digital circuit design or advanced mixed-signal IP implementation.
• Background in low-power digital design techniques.
• Hands-on experience implementing mixed-signal IPs (SerDes, DDR PHY, PLLs, DACs, ADCs, sensors).
• Experience developing automation and productivity scripts using Python or Perl.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related field is listed as the required credential in the role summary. The posting's minimum-qualification alternatives permit: a Bachelor's degree in science/engineering plus 2+ years of relevant ASIC design/verification/integration experience; or a Master's degree plus 1+ year of relevant experience; or a PhD in a related field. The posting also lists a PhD as a preferred qualification for more senior research/experience profiles.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.