DFx Verification

Job Title

DFx Verification

Role Summary

Senior DFx verification engineer within the Radeon Technologies Group front-end design/integration team. The role drives pre-silicon DFx (design-for-test/repair/observability) verification to achieve first-pass silicon success and supports correlation with post-silicon debug and bring-up.

Experience Level

Senior-level. Preferred experience: 8–10 years in DFx/DFT and digital verification.

Responsibilities

Primary responsibilities include planning, implementing, and executing DFx verification across block, subsystem, and SoC levels, and supporting post-silicon correlation and bring-up.

• Own DFx verification at block/IP, subsystem, and SoC levels (scan/ATPG, LBIST/MBIST, JTAG/1149.x, boundary scan, test compression, repair, debug).
• Develop and maintain SystemVerilog/UVM testbenches, tests, stimulus, checkers, coverage, and scoreboards for DFx features.
• Define and execute DFx verification plans from specs/requirements and track closure using coverage-driven metrics.
• Build and maintain BFMs, agents, and monitors to verify interactions between DFx logic and clocks, resets, power, fabric, and memories.
• Create directed and constrained-random tests for scan insertion, BIST, repair flows, test access, and debug/trace logic.
• Run gate-level simulations (including scan-inserted netlists with SDF) to validate DFx behavior, test modes, and power-up/reset sequences.
• Collaborate with DFT/DFx architects, RTL designers, and product engineers to review micro-architecture, identify corner cases, and drive DFx-friendly designs.
• Support post-silicon correlation, bring-up activities, pattern debug, and yield/quality improvements.
• Maintain and improve DFx regression, debug, and automation flows (scripting, dashboards, CI).

Requirements

Core technical skills and experience required or strongly preferred.

• Must-have: Strong experience in digital verification using SystemVerilog and UVM (or equivalent methodologies).
• Must-have: Hands-on experience with DFT/DFx concepts and flows such as scan, test compression, and ATPG patterns.
• Must-have: Proficiency in scripting for automation and regression (Python, Perl, Tcl, or Shell).
• Must-have: Proficiency in C/C++ and/or SystemVerilog DPI for modeling, test content generation, or reference models.
• Must-have: Experience running gate-level simulations, coverage analysis, and driving coverage closure.
• Nice-to-have: Experience with LBIST/MBIST, JTAG/IEEE 1149.x, boundary scan, on-chip debug/trace, and test access mechanisms.
• Nice-to-have: Experience with hardware emulation or FPGA prototyping, EDA ATPG/DFT tools, formal/lint flows, and silicon bring-up or production test.
• Nice-to-have: Background in SoC/CPU/GPU or high-performance graphics/compute ASICs.

Education Requirements

Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or equivalent technical degree (B.Tech / M.Tech). Academic credential is stated; equivalent practical experience is not explicitly listed in the posting.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.