DFT Technical Leader

Job Title

DFT Technical Leader

Role Summary

Join the Common Hardware Group to lead Design-for-Test (DFT) strategy and execution for next-generation Silicon One ASICs. You will collaborate with front-end RTL, verification, and physical-design teams to define, integrate, and validate DFT and test infrastructure across implementation and post-silicon phases.

Experience Level

Senior — requires significant experience; position requests at least 10 years of relevant experience.

Responsibilities

Primary responsibilities focus on DFT architecture, IP development, integration, and post-silicon validation.

• Define and implement hardware DFT features to support ATE, in-system test, debug, and diagnostics.
• Develop and integrate reusable DFT IP in coordination with RTL, verification, and physical design teams.
• Drive DFT requirements early in the design cycle and maintain testability through implementation and signoff.
• Support gate-level simulation, test-timing validation, and post-silicon debug workflows.
• Collaborate on DFT and physical-design aspects for die, stacked-die, and new silicon device models.
• Mentor or lead cross-functional teams on DFT methodology and infrastructure.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• At least 10+ years of hands-on experience in DFT, test, and silicon engineering.
• Experience with JTAG protocols, scan architectures, built-in self-test (BIST), memory BIST, and boundary scan.
• Working knowledge of ATPG and EDA tool flows (examples: Tetramax/TestMax, Tessent tool sets) and static timing tools such as PrimeTime.
• Experience with gate-level simulation and debugging (VCS or similar simulators).
• Post-silicon validation and debug experience, including ATE pattern workflows and P1687 usage.
• Ability to design solutions and debug complex hardware with minimal mentorship; strong cross-team communication skills.

Nice-to-have:

• Verilog/SystemVerilog design experience for custom DFT logic and IP integration.
• DFT CAD development experience covering test architecture, methodology, and infrastructure.
• Test static timing analysis and test-timing validation experience.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering is required (explicitly listed). The posting specifies the degree requirement in these fields with the 10+ years experience minimum.

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).