DFT Staff Engineer

Job Title

DFT Staff Engineer

Role Summary

Implement and own design-for-test (DFT) implementation for IP and SoC projects, including scan insertion, ATPG pattern generation, and fault simulation. Work with RTL designers and physical implementation teams to integrate DFT structures early, debug complex test failures, and support silicon bring-up and customer integrations. Mentor junior engineers and help establish scalable DFT methodologies.

Experience Level

Senior — typically requires 5+ years of hands-on DFT experience.

Responsibilities

Core responsibilities include end-to-end DFT implementation, cross-team integration, automation, and customer support during bring-up.

• Own end-to-end DFT implementation: scan chain insertion, stitching, ATPG pattern generation, and fault simulation.
• Develop and validate timing constraints for mission and test modes to ensure coverage without compromising performance.
• Collaborate with RTL design and physical implementation teams to integrate DFT structures early and avoid late-stage churn.
• Support IP integration and silicon bring-up: troubleshoot test failures and refine coverage strategies.
• Automate DFT workflows and post-processing using Perl, TCL, or Python to reduce manual effort.
• Debug complex scan and ATPG issues across large multi-million-gate designs using simulation and synthesis tools.
• Mentor junior engineers on DFT fundamentals, tools, and best practices.

Requirements

Concise list of must-have skills and a few desirable additions.

• Must-have: 5+ years of hands-on DFT experience with scan insertion, ATPG, JTAG, MBIST, and fault simulation.
• Proficiency with Synopsys DFT and verification tools such as DFTMAX, TetraMAX, VCS, and Design Compiler.
• Strong scripting skills in Perl, TCL, or Python for automating flows and post-processing results.
• Proven experience debugging timing violations, coverage gaps, and simulation mismatches in complex multi-clock domain designs.
• Experience working on large multi-million-gate designs and diagnosing ATPG/scan failures.
• Nice-to-have: experience with customer-facing IP integration or silicon bring-up and prior mentorship responsibilities.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.