DFT - Staff DFT Engineer

Job Title

Staff DFT Engineer

Role Summary

As a Staff DFT Engineer at an early-stage chiplet startup, you will define and implement DFT strategy and features across chip-level and IP blocks to meet manufacturability, test coverage, and performance goals. You will work closely with architects, AMS, validation, and operations to deliver test structures, patterns, and post-silicon bring-up for production.

Experience Level

Senior — 6-9 years of relevant industry experience.

Responsibilities

Primary responsibilities include defining and implementing DFT architecture, pattern generation and validation, lab bring-up, and supporting automation and production handoff.

• Define DFT strategy, methodologies, and implementation plans for chip-level and stand-alone IP blocks.
• Implement scan, memory BIST, and IEEE 1149.x/1687/1500/1838 structures in RTL for digital and analog blocks.
• Generate and validate patterns (e.g., 1687 PLDs, 1149.x, MBIST) at RTL and gate level.
• Generate ATPG patterns (SA/TDF/etc.) and validate in 0-delay and SDF-delay simulations.
• Collaborate with AMS teams to ensure DFT coverage for high-speed interfaces and structural tests in analog blocks.
• Work with circuit architects on advanced test techniques (PRBS PHY loopback, internal clock network measurement, etc.).
• Support flow automation and scripting for pattern generation and validation.
• Support device bring-up in the lab and pattern handoff to operations for ATE qualification, HTOL, and RMA analysis.
• Document overall test coverage and mitigation strategies.

Requirements

Must-have technical skills and experience; ideal qualifications are listed separately.

• Proficient in modern DFT/DFx techniques and tools (scan insertion, ATPG, MBIST).
• Working knowledge of industry standards (IEEE 1149.x, 1687, 1500, 1838).
• Proficient in Verilog simulation and debug of DFT structures at RTL and gate level.
• General knowledge of digital and analog/mixed-signal circuit design.
• Experience with tapeout and lab/ATE bring-up (specific counts summarized in Education Requirements).
• Proficient in TCL and shell scripting; working knowledge of Python, Perl, or similar; familiarity with standard build and tracking tools.
• Ability to work collaboratively with cross-functional teams and to document test coverage.
• Nice-to-have: delivery of hard/soft IP and design kit collaterals; experience balancing test time vs complexity vs coverage; Siemens Tessent platform experience.

Education Requirements

BS in Electrical Engineering (EE) or equivalent practical experience required; MS or PhD in EE (or equivalent) is preferred. The posting specifies 6–9 years of relevant industry experience and allows equivalent practical experience in lieu of formal degrees.

About the Company

Company: Eliyan

Headquarters: San Francisco, CA, USA

Early-stage chiplet startup developing technologies for chiplet-based systems, focused on delivering best-in-class power, area, manufacturability, and design flexibility. Works on DFT, IP, and test methodologies to enable high-volume, high-performance semiconductor products.