DFT - SCAN/ATPG

Job Title

DFT - SCAN/ATPG

Role Summary

Responsible for architecting and implementing DFX features (SCAN, ATPG, MBIST, BSCAN) for SoC and IP subsystems on the CDFX team. Work with RTL designers, verification, synthesis, place-and-route and product design teams to ensure correct DFT implementation and improve testability and debugability across AMD silicon.

Contribute to silicon testability and manufacturing readiness by delivering automated, scalable DFX solutions.

Experience Level

Mid-level (experienced ASIC/DFX engineer). No specific years of experience listed.

Responsibilities

Core responsibilities include design, integration, verification, automation, and debug of DFX features for complex ASICs.

• Lead DFX design architecture and implement SCAN, ATPG, MBIST, BSCAN and related features.
• Align DFX requirements with DFX architecture, IP design teams, RTL and verification groups.
• Design and develop correct-by-construction DFX and support DFX verification activities.
• Work with synthesis and place-and-route teams to ensure correct DFT implementation in Scan/ATPG flows.
• Develop and deploy automated design flows and scripts to scale DFX across SOCs and IP subsystems.
• Develop, debug, and characterize scan/ATPG patterns and at-speed (DC/AC) scan testing.
• Investigate failures, accelerate identification of functional defects, and improve debug processes.

Requirements

Key technical requirements and preferred skills.

• Must-have: Practical experience with ASIC DFX/DFT, scan synthesis, and ATPG at tile and SoC levels.
• Must-have: Strong hands-on debug skills and experience with scan/ATPG pattern development, verification, and characterization.
• Must-have: Proficiency in scripting (Perl, Python, TCL) to create automated flows and scalable solutions.
• Must-have: Experience with RTL quality/verification tools and methodologies (e.g., Spyglass, Lint) and exposure to static timing analysis and timing closure.
• Must-have: Strong communication and collaboration skills for working in a global cross-functional environment.
• Preferred: Experience with EDA/test tools such as Tessent/TestKompress, SSN, IJTAG, EDT, Synopsys Fusion Compiler, and Design Compiler.
• Preferred: Familiarity with scan compression techniques, failure mechanisms, IJTAG/TestKompress flows, and end-to-end DFX flow development.
• Preferred: Knowledge of low-power concepts (clock gating, power gating) and experience with DC/AC at-speed scan development and debug.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering with emphasis on SoC integration. The posting specifies these degrees; it does not explicitly state an "equivalent experience" clause.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.