DFT Principal Engineer

Job Title

DFT Principal Engineer

Role Summary

Senior hands-on DFT engineer responsible for defining and delivering design-for-test (DFT) architecture and implementation for complex SoCs from specification through tapeout. The role partners with customer and internal design teams across RTL, verification, physical implementation, and post-silicon validation to ensure production-quality testability and yield.

Experience Level

Senior - typically requires 10+ years of hands-on SoC DFT experience.

Responsibilities

Primary responsibilities include ownership of DFT strategy, implementation, and collaboration across functions to enable first-pass silicon success.

• Own DFT architecture, implementation, integration, and verification for complex SoCs and subsystems from spec through tapeout.
• Define and execute test strategies across scan/ATPG, memory BIST, logic BIST, and analog/PHY test to meet coverage, quality, yield, and cost targets.
• Identify testability risks early, propose practical RTL or design changes, and drive closure through signoff.
• Develop and institutionalize reusable DFT methodologies, checklists, and guidelines for use on active projects.
• Partner with silicon validation and test engineering on post-silicon debug, failure analysis, and pattern refinement.
• Collaborate with RTL design, functional verification, physical design, timing, and power teams to ensure testability is designed in.
• Provide technical guidance via design reviews, integration/debug support, and best-practice sharing.

Requirements

Concise list of required skills and proven experience; items labeled where appropriate.

• Must-have: 10+ years of hands-on SoC DFT experience with proven depth in scan/ATPG, memory BIST, and logic BIST implementation and integration.
• Must-have: Strong understanding of end-to-end SoC design flow from microarchitecture through RTL, synthesis, timing/physical implementation, and signoff.
• Must-have: Demonstrated track record owning DFT implementation for complex SoCs that have taped out and reached production; ability to balance test time, area/power overhead, and coverage.
• Must-have: Proven ability to work cross-functionally and drive resolution of testability issues under schedule constraints.
• Must-have: Experience with post-silicon debug and collaboration with test-engineering teams to refine production test programs.
• Nice-to-have: Working knowledge of Synopsys DFT tools such as TetraMAX, DFT Compiler, and BIST Architect.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related field (as stated in the posting).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.