DFT Lead Engineer

Job Title

DFT Lead Engineer

Role Summary

Senior DFT engineer responsible for leading DFT activities for ASIC/SoC designs from specification through implementation, verification, silicon bring-up, and production release. The role works with physical design, STA, test engineering, manufacturing, and customers to meet test and yield targets.

Experience Level

Senior - position expects extensive industry experience. The posting specifies 12+ years with a Bachelor's degree or 10+ years with a Master's degree.

Responsibilities

Primary responsibilities include architecture, implementation, verification, and production readiness of DFT features across ASIC projects.

• Define DFT specifications aligned with product test metrics and DPPM goals.
• Implement DFT (scan insertion, MBIST, TAP, LBIST, I/O DFT, SerDes integration, etc.).
• Generate, verify, simulate and debug ATPG/test vectors prior to tape-out.
• Work with STA and physical design teams to achieve DFT-mode timing closure.
• Validate and debug test vectors on ATE during silicon bring-up; assist failure analysis and yield improvement.
• Interface with customers and global PD, test, and manufacturing teams for debug and delivery.
• Automate DFT and test-vector generation flows and develop new DFT solutions for advanced process nodes (7nm+).

Requirements

Must-have technical skills and experience are listed first; nice-to-have items follow.

• Must-have: Strong DFT background including ATPG, scan, BIST, IO/analog DFT and test methodology.
• Experience with scan insertion and scan-compression tools (e.g., DFT Compiler, Mentor TestKompress).
• ATPG/vector generation, simulation and debugging experience (e.g., TetraMax, Fastscan).
• Verilog coding experience and testbench generation/simulation skills.
• Memory BIST insertion and verification (SRAM, CAM, eDRAM) and boundary-scan (IEEE 1149.1 / 1149.6) knowledge.
• Familiarity with Test-STA, constraints, and timing closure for test modes.
• Knowledge of IEE1687/IJTAG, ICL and PDL.
• Scripting/programming skills (TCL, Perl, Ruby, Python, C++ or similar) for automation.
• Strong debugging, root-cause analysis, and cross-disciplinary communication skills.
• Nice-to-have: ATE experience; experience with SerDes, DDR, PCIe, Ethernet, CXL IOBIST verification and silicon debug; experience with Tessent SSN; background in analog/digital circuit design and silicon/process fundamentals.

Education Requirements

Bachelor's degree in Electrical, Electronic, or Computer Engineering with 12+ years of relevant industry experience, or Master's degree in Electrical, Electronic, or Computer Engineering with 10+ years of relevant industry experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.