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August 27, 2026
Full-time
Remote friendly (San Francisco, California, United States)
Worldwide
DFT Jobs, Level - Senior

Job Title

DFT Lead

Role Summary

The DFT Lead will own design-for-test (DFT) strategy and execution for blocks and entire dies on the A-0 and A-1 wafer-scale systems. This role leads DFT activities across multiple tapeouts, drives sign-off criteria, and coordinates with design, verification, bring-up and yield teams.

Experience Level

Senior β€” expected to lead teams and projects. Prior experience leading DFT for multiple advanced-node SoC tapeouts is required; typically 7+ years in DFT/SoC design or equivalent experience.

Responsibilities

Primary responsibilities include planning, implementing, and validating DFT across complex SoC and wafer-scale designs.

  • Lead and own DFT strategy and delivery for blocks and full-die designs on wafer-scale systems.
  • Define DFT architecture, test plans, and sign-off criteria for scan, ATPG, BIST and other on-chip test mechanisms.
  • Develop and maintain DFT implementation flows, scripts, and automation to meet tapeout schedules.
  • Investigate and debug test failures in lab and silicon bring-up; support failure analysis and yield improvement.
  • Coordinate cross-functionally with RTL, physical design, verification, validation, and manufacturing teams.
  • Mentor and lead other DFT engineers; provide technical direction for tapeouts and design reviews.

Requirements

Must-have skills and experience to perform the role.

  • Proven experience leading DFT efforts for multiple advanced-node SoC tapeouts (must-have).
  • Strong knowledge of DFT methodologies: scan design, ATPG, fault models, compression, BIST and test access mechanisms.
  • Hands-on experience with industry DFT/ATPG tools and scripting to develop and automate flows.
  • Experience driving DFT sign-off and coordinating with cross-functional teams during tapeout.
  • Ability to debug test infrastructure, silicon failures, and collaborate on yield/run-time test solutions.

Nice-to-have:

  • Experience leading DFT for large die area (reticle-max) chips.
  • Experience with multi-die, chiplet, or MCM DFT strategies.
  • Experience with AI accelerator SoC DFT requirements and challenges.

Education Requirements

Not specified.


About the Company

Company: Volantis Semiconductor

Semiconductor hardware startup developing wafer-scale heterogeneous packages that integrate silicon and compound semiconductor dies for high-TDP AI platforms. Focus areas include advanced packaging design and process development, interposer technologies, thermal/mechanical challenges, and system co-design.

Volantis Semiconductor logo

Date Posted: 2026-08-26