DFT Implementation Engineer

Job Title

DFT Implementation Engineer

Role Summary

The DFT Implementation Engineer will design and implement Design-for-Test features (SCAN, MBIST, BSCAN, etc.) for SoCs and IP blocks. The role collaborates with architecture, design, verification, post-silicon, and manufacturing teams to deliver high-quality, testable silicon.

Primary focus areas include RTL and structural coding for DFT, test-content generation for manufacturing, and achieving test coverage and PPA objectives.

Experience Level

Mid-level. Requires approximately 5+ years of experience in DFT, SoC design, or related semiconductor design areas.

Responsibilities

Responsible for implementing and verifying DFT features and ensuring manufacturable test flow and coverage.

• Develop RTL and structural code to implement DFT features (SCAN, MBIST, BSCAN).
• Perform scan insertion, ATPG support, and test-content generation for high-volume manufacturing.
• Provide timing-closure support and address timing/test interactions.
• Collaborate on architecture and microarchitecture to integrate DFT into blocks, subsystems, and SoCs.
• Drive verification of DFT functionality and ensure design meets architecture/spec requirements.
• Support IP and SoC integration and handoff to manufacturing and post-silicon validation teams.
• Optimize designs for power, performance, area, timing, and test coverage targets.
• Document silicon learnings and iterate on test strategies to reduce defects-per-million (DPM).

Requirements

Must-have skills and experience; preferred items listed separately.

• 5+ years of experience in DFT, SoC design, or related semiconductor design roles.
• Hands-on experience with ATPG, scan insertion, and MBIST/repair flows.
• Experience with Tessent Shell flows and SSN methodology.
• RTL design experience in Verilog, VHDL, or SystemVerilog for DFT functionality.
• Experience generating manufacturing test content and working with ATE teams.
• Ability to work across cross-functional teams for IP and SoC integration.

Nice-to-have:

• Experience with Tessent Fast IO, ISTK, or similar advanced DFT toolsets.
• Familiarity with IEEE 1687 (IJTAG), IEEE 1149.1 (JTAG), IEEE 1500, IEEE 1838 and other DFT standards.
• Experience with industry DFT tools (Siemens EDA/Tessent, Synopsys DFT Compiler, Cadence Modus).
• Scripting for automation (TCL, Perl, Python).
• Knowledge of timing constraints, UPF, and low-power design/test methodologies.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is required.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.