DFT Engineer (Senior to Staff level)
QualcommJob Title
DFT Engineer (Senior to Staff level)
Role Summary
Join Qualcomm's central DFT methodology group to design, develop, and maintain design-for-test (DFT) flows and verification solutions for IPs, ASICs and SoCs. The role focuses on RTL-centric "shift-left" DFT methodology, automation, and end-to-end verification to improve testability and yield of complex semiconductor designs.
Experience Level
Senior to Staff level. Preferred experience: 10+ years working on complex SoC designs in RTL, DFT, or front-end engineering roles. Candidates with less experience may be considered for other senior technical roles.
Responsibilities
Key responsibilities include owning DFT methodology and automation, and supporting SoC/Block verification and test flows:
- Develop and maintain company-wide DFT methodologies, flows, and automation across business units.
- Architect RTL-centric DFT solutions and advanced DFT/DFD features; implement RTL where vendor tools lack support.
- Create automated verification testbenches and sequence generation for DFT IP; define end-to-end verification strategies including static checks, formal and sequence-based approaches.
- Build IP/block and SoC level scan insertion flows; script ATPG retargeting and create QoR checks for implementation quality control.
- Write static timing constraints, manage waivers, and develop flows for robust timing verification of DFT logic and test sequences.
- Collaborate with cross-functional teams (RTL designers, verification, CAD/automation, packaging) to integrate custom DFT logic and support bring-up and yield improvement.
Requirements
Core technical requirements and preferred skills. Education requirements are listed separately below.
- Must-have: Extensive experience (typically 10+ years) with complex SoC designs in RTL and DFT domains.
- Must-have: Strong knowledge of Verilog/VHDL and SystemVerilog; RTL coding for DFT features.
- Must-have: Hands-on experience with major DFT/EDA tool flows from Siemens, Synopsys, and Cadence.
- Must-have: Practical experience with scan insertion, ATPG, test simulation (zero-delay), and SDF-annotated test sequences.
- Must-have: Deep familiarity with DFT standards and techniques: JTAG (1149.1/1149.6/1500), iJTAG (1687), and memory/logic/interconnect BISTs.
- Must-have: Experience in CAD/automation and scripting for DFT flows; knowledge of TCL and Python; experience with Perl-style text processing is useful.
- Nice-to-have: Track record integrating custom DFT logic for complex SoCs and advanced packaging (e.g., CoWoS) and experience retargeting ATPG for implementation constraints.
- Nice-to-have: Experience architecting verification solutions across static checks, formal methods, and sequence-based verification.
Education Requirements
Degrees accepted: Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related technical fields. The posting lists typical minimums such as a Bachelor's plus additional hardware engineering experience (e.g., Bachelor's +2 years or Master's +1 year) up to PhD-level qualifications.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
