DFT Engineer, Principal
QualcommJob Title
DFT Engineer, Principal
Role Summary
Principal member of Qualcomm's central Design-for-Test (DFT) methodology group. Responsible for architecting, developing and supporting DFT flows and verification solutions for IPs, ASICs and SoCs across business units.
Work focuses on RTL-centric "shift-left" DFT methodology, building automated flows, verification infrastructure, and integrations to meet quality and manufacturability goals.
Experience Level
Senior / Principal level. The posting indicates senior-level experience - typically 8+ years; degree-linked minima are provided in Education Requirements (Bachelor's +8 years, Master's +7 years, PhD +6 years). The role expects candidates with roughly 8–10+ years of relevant SoC/DFT experience.
Responsibilities
Core responsibilities include developing methodology, automation and verification for DFT across blocks and SoCs.
- Develop and maintain central DFT methodology and flows used across business units and projects.
- Architect RTL-centric, "shift-left" DFT solutions for IPs, ASICs and SoC designs.
- Write and automate RTL for advanced DFT/DFD features beyond vendor tool support.
- Create automated verification testbenches, sequences and end-to-end verification solutions (static checks, formal, and sequence-based verification).
- Build IP/block and SoC-level scan insertion flows and ATPG retargeting procedures.
- Implement automated QoR checks and flows for design quality control.
- Produce static timing constraints, manage waivers, and define flows for robust timing verification.
Requirements
Must-have technical skills and experience for successful performance in this role.
- Extensive experience with DFT EDA tool flows from major vendors (Siemens, Synopsys, Cadence).
- Proficient in RTL and verification languages: Verilog/VHDL and SystemVerilog.
- Proven track record in SoC DFT integration, scan insertion, ATPG, and simulation including SDF-annotated sequences.
- Deep familiarity with DFT standards and techniques: JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST (memory, logic, interconnect).
- Experience building automated flows, CAD/EDA automation and retargeting ATPG procedures.
- Ability to design and verify custom DFT logic for complex SoC and advanced packaging (CoWoS) designs - highly desirable.
- Nice-to-have: scripting and automation skills (Perl/Tcl/Python), formal verification exposure, and experience refactoring legacy automation code.
Education Requirements
Graduation-level technical degree expected: Bachelor's in Computer Science, Electrical/Electronics Engineering, Engineering or related field (with ~8+ years relevant experience); OR Master's in those fields (~7+ years); OR PhD in those fields (~6+ years). The posting also references relevant work experience in lieu of a degree.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
