DFT Engineer

Job Title

DFT Engineer

Role Summary

Work on DFT architecture, implementation, verification, and signoff for complex SoC and ASIC designs at advanced process nodes. The role interfaces with RTL, verification, physical design, test engineering, and EDA vendors to ensure manufacturable, testable silicon.

Experience Level

Senior — experience range listed as approximately 3–12 years in DFT engineering.

Responsibilities

Deliver DFT solutions across design phases and support silicon bring-up and production test.

• Develop and implement DFT architectures for SoC/ASIC designs.
• Perform scan insertion, scan compression, and ATPG generation.
• Analyze and improve fault coverage for manufacturing tests.
• Implement and support JTAG, Boundary Scan, MBIST, and LBIST.
• Collaborate with RTL, verification, physical design, and test teams.
• Execute DFT verification using simulation and formal methods.
• Drive DFT signoff and debug scan-chain, ATPG, and silicon bring-up issues.
• Support post-silicon validation and production test activities.
• Work with EDA vendors to optimize DFT flows.

Requirements

Core technical requirements and preferred skills.

Must-have:

• 3–12 years of DFT engineering experience for ASIC/SoC development.
• Strong knowledge of Scan Architecture, ATPG, and fault models.
• Hands-on experience with scan insertion and scan compression techniques.
• Experience with JTAG, Boundary Scan, MBIST, and LBIST methodologies.
• RTL design familiarity using Verilog/SystemVerilog and ASIC flow (RTL to GDSII).
• Strong debugging and problem-solving skills for pre- and post-silicon issues.
• Experience with industry EDA tools such as Synopsys DFT Compiler, Synopsys TetraMAX/TestMAX, Cadence Modus/Tessent, PrimeTime, VCS/Xcelium, and debugging/visibility tools (Verdi/SimVision).

Nice-to-have:

• Experience with advanced process nodes (16nm, 7nm, 5nm, 3nm).
• Exposure to low-power DFT methodologies.
• Knowledge of IEEE 1500 and IEEE 1687 standards.
• Understanding of timing closure and physical-design impacts on DFT.
• Experience with high-performance CPU, GPU, AI/ML, networking, or automotive SoCs.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (as stated).

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.