DFT Engineer

Job Title

DFT Engineer

Role Summary

Senior verification engineer responsible for planning and executing DFT verification for ASIC designs, working with DFT design and manufacturing engineers to deliver reliable silicon. The role focuses on building coverage-driven verification environments, debugging issues from RTL through gate-level, and supporting post-silicon bring-up.

Experience Level

Senior — typically 5+ years in digital design verification with at least 2 years focused on DFT verification.

Responsibilities

Key responsibilities include developing verification infrastructure, executing verification plans, and collaborating with design and manufacturing teams to close verification:

• Develop and maintain RTL verification environments using UVM or equivalent methodologies.
• Create and execute coverage-driven verification plans aligned with design specifications.
• Use EDA DFT tools to generate and run MBIST and scan testcases and validate inserted DFT fabric.
• Develop directed tests for non-vendor-supplied DFT logic and validate corner cases.
• Verify ATPG patterns at SoC level and validate manufacturing reset sequences.
• Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis.
• Implement and track functional and code coverage and drive verification to closure.
• Write reusable verification components and SystemVerilog Assertions (SVA); automate regression with Python and scripting.
• Participate in design and verification reviews and support post-silicon test bring-up debug.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

Must-have:

• 5+ years in digital design verification with at least 2 years in DFT verification.
• Hands-on experience with SystemVerilog and UVM (or equivalent) verification methodologies.
• Experience with industry EDA simulators (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium) and DFT tools (e.g., Synopsys TestMax/Yield Accelerator, Siemens Tessent).
• Experience with gate-level simulation and tester pattern formats such as STIL.
• Scripting and automation proficiency (preferably Python).
• Experience verifying test sequences for high-speed PHY logic (PCIe, Ethernet 10G/40G/100G).
• Strong analytical, problem-solving, and communication skills; ability to work independently and manage tasks to completion.

Nice-to-have:

• Experience with SoC-level verification.
• Familiarity with change control systems (git).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.