DFT Engineer

Job Title

DFT Engineer

Role Summary

Work on design-for-test (DFT) for FPGA devices, focusing on scan insertion, ATPG pattern generation, and test verification at block level with growing ownership of top-level flows. Collaborate with design, verification, and test teams to improve test coverage, product quality, and test-cost efficiency.

Experience Level

Mid-level. Typical candidates have 1–5 years of relevant DFT or related industry or academic experience.

Responsibilities

Primary responsibilities include block-level DFT implementation, ATPG generation and verification, and supporting silicon bring-up and test engineering.

• Execute scan insertion and generate ATPG patterns at block level; support top-level flows as experience grows.
• Perform ATPG generation, pattern simulation, and verify test patterns to improve coverage and quality metrics.
• Debug DFT circuitry, timing, and simulation issues in collaboration with design and verification teams.
• Use industry EDA tools (Tessent, Synopsys, Cadence) within established ATPG flows and expand FPGA-specific test methodology knowledge.
• Contribute to backend ATPG activities, HVM test content development, and ATE bring-up to support yield and product quality objectives.
• Analyze test cost vs. coverage and propose practical improvements to the DFT flow.

Requirements

Must-have skills and experience first; nice-to-have items listed where applicable.

• Must: 1–5 years of experience with DFT concepts, scan architecture, pattern generation, and fault simulation (or equivalent practical/academic experience).
• Must: Practical understanding of scan insertion and ATPG generation; hands-on experience preferred but strong coursework or internship exposure is acceptable.
• Must: Familiarity with EDA ATPG tools (Tessent, Synopsys, Cadence) and willingness to expand tool expertise.
• Must: Strong analytical and problem-solving skills and a proactive approach to learning FPGA-specific DFT techniques.
• Nice-to-have: Exposure to ATE environments, test program development, pattern formats, and silicon bring-up activities.
• Successful background and reference checks are required.
• Right to work in Malaysia is required for this position.

Education Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field is preferred. Equivalent practical experience or strong academic grounding (relevant coursework or internships) is explicitly considered for junior candidates.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.