DFT Engineer

Job Title

DFT Engineer

Role Summary

Design, implement, and sign off Design-for-Test (DFT) architecture for complex SoCs and IP blocks to ensure manufacturable, testable silicon while balancing coverage, performance, power, and cost.

Position works across RTL, physical design, and verification teams to integrate scan, BIST, boundary-scan, and compression solutions into the chip design and signoff flows.

Experience Level

Senior / Staff-level DFT engineer (senior technical responsibility). No explicit years-of-experience specified.

Responsibilities

Primary responsibilities include architecture, implementation, verification, and cross-functional integration of DFT solutions:

• Define and implement DFT architecture at block/IP and SoC level; specify test methodologies (scan, MBIST/LBIST, boundary scan, compression).
• Ensure testability is designed into RTL and system integration early in the flow.
• Perform scan insertion, stitching, and ATPG pattern generation and simulation.
• Integrate MBIST/LBIST and boundary-scan infrastructure; validate patterns via simulation and test tools.
• Develop and validate DFT timing constraints and run STA for DFT paths; execute RTL and gate-level DFT flows.
• Analyze and improve fault coverage; debug scan/ATPG issues and resolve coverage holes.
• Optimize pattern count, test time, and overall test cost.
• Run DFT verification and DRC checks and drive clean DFT signoff considering coverage, timing, and power impact.
• Collaborate with RTL designers, physical design, and verification teams to support SoC-level DFT integration and guidelines.

Requirements

Must-have technical skills and tools:

• Proven end-to-end DFT implementation experience (architecture through signoff).
• Scan insertion & compression and ATPG experience; MBIST/LBIST and boundary/JTAG integration.
• DFT signoff, fault coverage analysis, and scan/ATPG debugging skills.
• Strong RTL and SoC design-flow understanding and familiarity with STA for DFT paths.
• Experience with industry tools such as Siemens Tessent, Synopsys TestMAX, Cadence Modus (or equivalent).
• Scripting proficiency (TCL, Python, Perl) to automate DFT flows and analyses.

Nice-to-have:

• Experience with pattern compression techniques and test cost optimization at SoC level.
• Prior work on large SoC DFT integration and cross-team coordination.

Education Requirements

Not specified.

About the Company

Company: Cadence

Headquarters: San Jose, California, United States

Cadence develops electronic design automation (EDA) software and hardware for designing integrated circuits, systems-on-chip, and printed circuit boards, offering tools for verification, synthesis, simulation, and signoff across semiconductor and electronics industries.