DFT Engineer

Job Title

DFT Engineer

Role Summary

Design-for-test (DFT) engineer responsible for implementing and validating testability features for ASIC/SoC projects. Works with RTL, validation, and physical teams to deliver ATPG patterns, memory built-in self-test (MBIST) solutions, IO and clock test strategies, and debug test failures.

Experience Level

Mid-level — requires 5+ years of hands-on DFT/ATPG experience.

Responsibilities

Primary responsibilities include designing, implementing, and verifying DFT solutions across the chip development lifecycle.

• Develop and integrate scan architectures and DFT structures for SoC/ASIC designs.
• Generate, analyze, and debug ATPG patterns and fault coverage results.
• Design and validate MBIST and memory test architectures and diagnostics.
• Define and execute IO and pin-level test strategies and validation.
• Implement clock DFT features and perform clock-domain test verification.
• Work with RTL and validation teams to diagnose test failures and improve testability.
• Use industry-standard DFT/ATPG EDA tools to deliver test solutions on schedule.

Requirements

Must-have technical skills and experience.

• 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs.
• Strong understanding of DFT fundamentals including controllability and observability and scan-based testing.
• Proven expertise in ATPG pattern generation, analysis, and debug.
• Experience with MBIST, memory test architectures, and diagnostics.
• Knowledge of IO test methodologies for interface and pin-level validation.
• Solid understanding of clock DFT and clock verification concepts.
• Strong grasp of digital design and RTL fundamentals.
• Experience with industry-standard DFT/ATPG EDA tools.
• Ability to work effectively in fast-paced semiconductor programs and strong analytical, problem-solving, and communication skills.

Education Requirements

Bachelor of Engineering (BE) required.

About the Company

Company: ForwardEdge ASIC

Engineering company focused on ASIC and FPGA design and verification, providing verification strategy, testbench development, and technical leadership for complex high-performance chip designs. Supports projects requiring US government security clearances.