DFT Engineer

Job Title

DFT Engineer

Role Summary

Work on pre-silicon and post-silicon verification of ASIC DFT logic to ensure functionality, testability, and manufacturability of silicon. Collaborate with DFT design and manufacturing engineers to develop verification environments, execute coverage-driven plans, and support silicon bring-up.

Experience Level

Mid-level — typically 5+ years of digital design verification experience, including at least 2 years focused on DFT verification.

Responsibilities

Deliver verification for DFT logic from planning through closure and support post-silicon debug when required.

• Develop and maintain RTL verification environments using UVM or equivalent methodologies.
• Create and execute coverage-driven verification plans aligned to specifications.
• Use EDA DFT tools (e.g., TestMax, Tessent) to generate and run MBIST and scan-related pre-silicon tests.
• Develop directed tests for non-vendor DFT logic and exercise corner cases.
• Verify ATPG patterns at SoC level and validate manufacturing reset sequences.
• Analyze simulation results, debug complex issues, and perform root-cause analysis with design and manufacturing teams.
• Implement and track functional and code coverage; drive verification to closure.
• Develop reusable verification components and write SystemVerilog Assertions (SVA).
• Automate regressions and improve verification infrastructure using Python and scripting.
• Participate in design and verification reviews to improve testability and correctness.

Requirements

Must-have technical skills and experience for immediate contribution.

• 5+ years in digital design verification, with at least 2 years in DFT verification.
• Proficient in SystemVerilog and UVM-based or similar verification methodologies.
• Experience with industry simulators (Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium).
• Hands-on with EDA DFT tool flows (e.g., Synopsys TestMax/Yield Accelerator, Siemens Tessent) and gate-level simulation; familiarity with tester pattern formats such as STIL.
• Experience verifying test sequences for high-speed PHYs (PCIe, Ethernet 10G/40G/100G).
• Strong scripting and automation skills (Python preferred).
• Solid digital design fundamentals, debugging skills, and coverage-driven verification practice.
• Clear written and verbal communication; ability to work independently and manage tasks to completion.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field as stated in the posting.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.