DFT Engineer

Job Title

DFT Engineer

Role Summary

Design-for-Test (DFT) engineer responsible for implementing and verifying DFT features to ensure silicon testability and manufacturability. Work with chip design, place-and-route, and test teams to insert scan, MBIST, and IJTAG infrastructure and produce test collateral.

Experience Level

Mid-level. Years of experience not specified.

Responsibilities

Primary responsibilities focus on DFT implementation, verification, and test collateral generation across digital and IO subsystems.

• Insert and verify DFT features: SCAN (with SSN), JTAG/Boundary Scan, and MBIST.
• Implement MBIST repair and validate repair mechanisms.
• Generate test collateral for timing, and coordinate with place-and-route for test insertion.
• Work with DFx and test teams to define and validate Test Timing and test flows.
• Apply IJTAG (IEEE 1687) standards and author/interpret ICL and PDL specifications.
• Verify high-speed IO testability and integration with DFT structures.

Requirements

Technical must-haves and desirable skills for effective performance in this role.

• Must-have: Practical experience with DFx/DFT techniques including SCAN insertion and MBIST implementation and verification.
• Must-have: Familiarity with Siemens suite of DFT tools (or equivalent toolchains).
• Must-have: Experience implementing MBIST repair and validating repair flows.
• Must-have: Knowledge of IJTAG (IEEE 1687) and ability to work with ICL/PDL specifications.
• Must-have: Ability to verify DFT features such as Boundary Scan, JTAG, SCAN, MBIST, and high-speed IO testability.
• Nice-to-have: ATPG experience (the client notes ATPG is not mandatory).

Education Requirements

Not specified.

About the Company

Company: DensityAI

Headquarters: Mountain View, CA, United States

DensityAI is a semiconductor company focused on developing advanced silicon and multi-die packaged chips, with expertise in design-for-test, verification, and production test for high-performance and AI applications.