DFT Engineer

Job Title

DFT Engineer

Role Summary

Design and implement design-for-test (DFT) architecture for a multi-chip SoC, covering scan, BIST, memory repair, and boundary-scan (ACJTAG/DCJTAG). Work with synthesis constraints and collaborate with logic and physical design to meet testability, performance, and power goals. Supervise ATPG flows and ensure high scan and at-speed coverage targets.

Experience Level

Mid-level. Specific years of experience not stated; role expects prior ASIC/DFT experience and multiple tape-outs in advanced nodes.

Responsibilities

Key responsibilities include:

• Define DFT architecture for a multi-chip system SoC and drive test strategy across chips.
• Implement scan-based test infrastructure and supervise ATPG generation to achieve high coverage, including at-speed scan.
• Develop and integrate BIST, memory repair, and boundary-scan (ACJTAG/DCJTAG) solutions.
• Specify and apply synthesis constraints (SDC) and participate in synthesis flows affecting testability.
• Implement on-chip controllers (OCC) and advanced DFT techniques such as LBIST and streaming where applicable.
• Perform RTL and gate-level simulation for verification of test logic and flows.
• Work with serializers/deserializers and support interactions between logic and physical design to meet low-power and high-performance targets.
• Collaborate with CAD/DFT tool workflows (Mentor/Synopsys) and supervise tool-driven flows and scripts.

Requirements

Must-have and preferred technical qualifications:

• Must have: Strong proficiency with Mentor or Synopsys test/DFT tool flows and ATPG generation.
• Must have: Practical experience with scan design, BIST, memory repair and boundary-scan methodologies.
• Must have: Proficiency in synthesis constraints (SDC) and familiarity with synthesis-related impacts on DFT.
• Must have: Fluent in RTL and gate-level simulation; experience achieving at-speed scan coverage.
• Must have: Scripting experience (Unix, Perl, Python, TCL) to automate flows and tool integration.
• Preferred: Exposure to advanced DFT techniques (LBIST, streaming) and experience with serializers/deserializers.
• Preferred: Prior experience with EMIB architectures and multi-chip bridge designs.
• Preferred: Multiple tape-outs in deep sub-micron process nodes (7nm or below) and understanding of device physics at advanced nodes.

Education Requirements

Not specified.

About the Company

Company: TetriQ Solutions

Headquarters: Saratoga, CA, USA

Technology staffing and solutions provider specializing in engineering placements and technical consulting for semiconductor, software, and hardware domains.