DFT Engineer

Job Title

DFT Engineer

Role Summary

Senior DFT (design-for-test) verification engineer responsible for planning and executing coverage-driven verification for ASIC DFT logic, building verification environments, and collaborating with DFT design and manufacturing engineers to deliver reliable silicon.

Work with DFT features including scan/ATPG, MBIST, boundary scan, memory repair, and fuseboxes; support pre-silicon verification and post-silicon debug.

Experience Level

Senior — typically 5+ years in digital design verification with at least 2 years focused on DFT verification.

Responsibilities

Primary responsibilities include developing verification environments, executing verification plans, analyzing results, and driving closure.

• Develop and maintain RTL verification environments using UVM or equivalent methodologies.
• Create and execute coverage-driven verification plans aligned with specifications.
• Use EDA DFT tools to generate and run MBIST and scan fabric test cases; develop directed tests for other DFT logic.
• Verify ATPG patterns at SoC level and validate manufacturing reset and test sequences.
• Analyze simulations, debug complex issues, and perform root-cause analysis with design engineers.
• Implement and track functional and code coverage to drive verification to closure.
• Develop reusable verification components and write SystemVerilog Assertions (SVA).
• Automate regression testing and improve verification infrastructure using Python and scripting.
• Participate in design/verification reviews and support post-silicon bring-up debug with DFT designers.

Requirements

Must-have technical skills and experience; a few desirable skills are listed separately.

• Must-have: 5+ years in digital design verification with at least 2 years focused on DFT verification.
• Must-have: Strong hands-on experience with SystemVerilog and UVM (or similar) methodologies.
• Must-have: Experience with EDA simulation tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium) and DFT tool flows (e.g., Synopsys TestMax/Yield Accelerator, Siemens Tessent).
• Must-have: Experience with gate-level simulation and tester pattern formats such as STIL.
• Must-have: Scripting and automation experience (preferably Python).
• Must-have: Verification experience for high-speed PHY logic (PCIe, Ethernet 10G/40G/100G).
• Must-have: Strong analytical, debugging, and communication skills; ability to work independently and manage tasks to completion.
• Nice-to-have: Experience with change control systems (git) and SoC-level verification.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: DensityAI

Headquarters: Mountain View, CA, United States

DensityAI is a semiconductor company focused on developing advanced silicon and multi-die packaged chips, with expertise in design-for-test, verification, and production test for high-performance and AI applications.