DFT Design & Methodology Development Engineer

Job Title

DFT Design & Methodology Development Engineer

Role Summary

Lead the Design-for-Test (DFT) strategy for the 2nm digital reference flow, integrating Scan and MBIST tools and driving next-generation DFT methodology adoption for advanced GAA designs. Work across synthesis and place-and-route stages and coordinate with EDA vendors and design partners to ensure high testability and efficient yield ramp.

Experience Level

Senior-level (lead role). Years of experience not specified.

Responsibilities

Primary responsibilities include:

• Integrate Scan and MBIST into the digital reference flow and validate tool flows.
• Evaluate and implement advanced DFT technologies (e.g., Streaming Scan Network) to reduce test data volume and test time.
• Develop and validate ATPG methodologies using cell-aware (intra-cell) fault models to achieve high defect coverage at 2nm.
• Conduct feasibility studies for new failure-analysis methodologies to improve yield ramp-up.
• Collaborate with EDA vendors to implement advanced DFT features and with design partners for pattern generation and silicon-based diagnosis.
• Support DFT implementation and pattern execution for internal Rapidus test chips.
• Provide customers and partners with DFT guidelines and technical support.
• Lead adoption of automation tools, including AI/ML-driven design-space exploration (DSE), for DFT flows.

Requirements

Key technical and collaboration requirements:

• Must-have: Solid understanding of DFT methodologies: Scan, MBIST, and ATPG.
• Must-have: Proven ability to work with EDA vendors and external design service partners.
• Nice-to-have: Experience with advanced process nodes (7nm FinFET and beyond) or challenges related to GAA/2nm.
• Nice-to-have: Familiarity with advanced DFT architectures (SSN, packetized test) and cell-aware testing.
• Experience in failure analysis and yield-improvement activities.
• Experience with automation and AI/ML-driven tools for DFT or DSE is a plus.
• Professional proficiency in English; Japanese language skills are a plus.

Education Requirements

BS, MS, or PhD in Electrical Engineering or a related technical field, or equivalent practical experience.

About the Company

Company: Rapidus

Headquarters: Tokyo, Japan

Japan-led semiconductor initiative founded in 2022 to build a world-class advanced logic foundry. Focuses on R&D, design enablement, and manufacturing of cutting-edge logic semiconductors including 2nm and next-generation process technologies.