DFT (Design for Test) Engineer / Design Engineer

Job Title

DFT (Design for Test) Engineer / Design Engineer

Role Summary

Contract DFT engineer responsible for implementing and validating design-for-test features on digital ASIC projects. Work includes ATPG, MBIST, clock DFT, IO testing and scan methodologies using industry DFT tools.

Based in Santa Clara, CA with on-the-road travel expected to support bring-up, validation, and cross-team integration.

Experience Level

Mid-level — 3–11 years of relevant experience (job specifies overall 3–11 years).

Responsibilities

Primary responsibilities include:

• Implement and integrate DFT features (scan insertion, boundary-scan/JTAG, IJTAG).
• Run ATPG: generate test patterns, analyze/debug patterns, and improve fault coverage.
• Design, implement and validate MBIST architectures and memory diagnostics.
• Perform IO-level and pin validation tests and debug interface issues.
• Work on clock DFT and clock-tree verification related to testability.
• Verify DFT features in RTL (Verilog/SystemVerilog) and support silicon bring-up.
• Collaborate with RTL designers, verification teams, and manufacturing/test groups to resolve test failures.

Requirements

Must-have skills and experience:

• Hands-on experience with Siemens Tessent (Mentor Graphics) DFT tool suite.
• Solid understanding of DFT fundamentals: controllability, observability, scan insertion, scan-based testing.
• Proven ATPG experience: pattern generation, analysis, debugging, fault-coverage improvement.
• Experience with MBIST: memory test architecture, implementation, and diagnostics.
• Knowledge of IO test methodologies and clock DFT/verification concepts.
• Strong digital design background and RTL experience (Verilog/SystemVerilog).
• Experience verifying DFT features including Boundary Scan (JTAG), IJTAG, and high-speed scan testing.
• Excellent analytical, debugging, and problem-solving skills.
• Minimums noted in source: at least 1 year using DFT tool suite and 1 year design engineering experience; overall experience range 3–11 years.

Nice-to-have:

• Experience with multiple industry-standard DFT/ATPG EDA tools beyond Tessent.
• Previous silicon bring-up and lab test experience.

Education Requirements

Not specified.

About the Company

Company: Northern Base

Recruitment and staffing firm focused on placing engineering and technology professionals in contract and permanent roles, often supporting semiconductor and electronics industry hiring needs.