Job Title
DFT (Design for Test) Engineer
Role Summary
Implement and validate design-for-test solutions for digital ASIC/SoC projects. Work with RTL designers and verification teams to develop ATPG, MBIST, scan insertion, IO and clock test strategies, and to diagnose and resolve test failures.
Experience Level
Mid-level. No specific years of experience listed.
Responsibilities
Primary responsibilities include:
- Develop and apply DFT strategies and test architectures using Siemens Tessent and other EDA DFT tools.
- Create, analyze and debug ATPG patterns; improve fault coverage and test quality.
- Design and verify MBIST implementations and memory diagnostics.
- Perform scan insertion and validate boundary scan (JTAG/IJTAG) and high-speed scan testing.
- Validate IO test methodologies and perform pin-level interface testing.
- Verify clock DFT and clock-domain testability, and address clock-related test issues.
- Collaborate with RTL and verification teams to ensure testability and to troubleshoot failures.
- Produce test reports, metrics and documentation for manufacturing and validation teams.
Requirements
Must-have:
- Hands-on experience with Siemens Tessent (Mentor Graphics) DFT tool suite.
- Strong knowledge of DFT fundamentals: controllability, observability, scan insertion, scan-based testing.
- Proven ATPG experience: pattern generation, analysis, debugging, and fault coverage improvement.
- Experience with MBIST architecture, implementation and diagnostics.
- Familiarity with IO test methodologies and pin-level validation.
- Understanding of clock DFT and clock verification concepts.
- Solid digital design and RTL knowledge (Verilog/SystemVerilog).
- Experience verifying DFT features including Boundary Scan (JTAG), IJTAG, MBIST, and high-speed scan testing.
- Strong analytical, debugging and problem-solving skills.
Nice-to-have:
Education Requirements
Not specified.
About the Company
Company: INFT Solutions
Provides engineering staffing and contract services for semiconductor and electronics companies, including design, verification, and test support such as DFT and ATPG expertise.

Date Posted: 2026-07-23