DFT Design Engineer

Job Title

DFT Design Engineer

Role Summary

Design and implement Design-for-Test (DFT) solutions for IP and SoC programs to ensure manufacturability, test coverage, and silicon quality. Work on DFT infrastructure, test methodologies, and silicon bring-up while collaborating with design, verification, physical design, product engineering, manufacturing test, and IP teams.

Experience Level

Senior — typically 10+ years experience with a Bachelor's degree or 8+ years with a Master's degree (see Education Requirements for details).

Responsibilities

The engineer will deliver DFT implementations and verification across design lifecycles and drive test readiness and signoff.

• Design, implement, validate, and debug DFT solutions across IP and SoC programs.
• Develop and validate TAP/JTAG and IJTAG (IEEE 1687) infrastructures and Boundary Scan (IEEE 1149.1).
• Implement and validate MBIST, scan insertion, scan compression, and ATPG methodologies.
• Generate ATPG patterns and test collateral (ICL, PDL, BSDL) and optimize coverage.
• Validate RTL and Gate-Level Simulation (GLS) for DFT features and perform root-cause analysis of DFT failures.
• Perform memory test validation and debug scan, at-speed, and silicon bring-up issues.
• Collaborate with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness and signoff.
• Lead technical reviews, adopt DFT best practices, and drive continuous process improvements.

Requirements

Must-have technical skills and experience; formal degree and years-of-experience are listed under Education Requirements.

• Proven experience with TAP/JTAG and IJTAG (IEEE 1687) and Boundary Scan (IEEE 1149.1).
• Hands-on experience with MBIST, scan insertion, scan compression, and ATPG.
• Proficiency in Verilog/SystemVerilog and DFT verification methodologies.
• Scripting skills: Tcl, Perl, and/or Python for automation and tooling.
• Experience with RTL design for DFT and Gate-Level Simulation validation.
• Experience in pattern generation, coverage optimization, and memory test validation.
• Silicon debug experience including at-speed and bring-up issue resolution.
• Strong communication skills and ability to lead technical reviews and collaborate across teams.

Education Requirements

Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related field with 10+ years of relevant experience; OR Master's degree in Electrical Engineering, Microelectronics, VLSI, or related field with 8+ years of relevant experience.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.