DFT Design Engineer

Job Title

DFT Design Engineer

Role Summary

SoC/ASIC digital design engineer specializing in Design for Test (DFT). The role focuses on implementing scan insertion, compression scan technologies, memory BIST, and producing ATPG patterns to meet fault coverage targets.

Works within a DFT/SoC team collaborating with architecture, design, verification, and customers to deliver testable silicon. Positions based in Austin or San Jose; full-time.

Experience Level

Mid-level — 3 to 12 years of professional SoC/ASIC digital design experience with a focus on DFT.

Responsibilities

Key responsibilities include design, implementation, verification, and debug of DFT features and test patterns.

• Design and implement DFT insertion flows for SoC/ASIC projects.
• Perform scan chain insertion using synthesis or DFT tools.
• Implement compression scan insertion and LBIST strategies.
• Develop and validate memory built-in self-test (MBIST) solutions.
• Generate ATPG patterns to achieve and measure test coverage goals, using metrics-driven approaches.
• Debug test failures and analyze faults to improve coverage and robustness.
• Verify ATPG testbenches and investigate simulation mis-compares.
• Collaborate with cross-functional teams (Architecture, Design, Internal and External customers) and deliver DFT tasks independently.

Requirements

Must-have technical skills and experience; followed by desirable qualifications.

• 3–12 years of professional experience in SoC/ASIC digital design with a focus on DFT.
• Practical experience with scan-chain insertion and DFT insertion flows.
• Experience with compression scan technologies and LBIST.
• Strong knowledge of memory BIST (MBIST) techniques.
• Expertise in Automatic Test Pattern Generation (ATPG) and meeting coverage targets.
• Experience debugging test failures and analyzing fault coverage metrics.
• Familiarity with JTAG (IEEE 1149.1/6), IEEE 1500, and IEEE 1687.
• Ability to work independently and collaboratively in cross-functional teams; strong problem-solving and methodical approach.

Nice-to-have:

• Prior experience with Cadence tools and flows.
• Knowledge of timing analysis and equivalency checking.
• Hands-on experience with synthesis, verification, and debugging Verilog testbenches.
• US citizenship preferred.

Education Requirements

Not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.