DFT Design Engineer

Job Title

DFT Design Engineer

Role Summary

Work on SoC/ASIC Design-for-Test (DFT) implementation and verification to meet production testability and coverage goals. The role focuses on scan chain insertion, compression scan technologies, MBIST, and ATPG, and involves debugging test failures and verifying ATPG testbenches.

Collaborate with architects, RTL designers, verification teams, and internal/external customers to deliver DFT solutions using established flows and tools.

Experience Level

Mid-level — typically 3 to 12 years of professional experience in SoC/ASIC digital design with a focus on DFT.

Responsibilities

Primary responsibilities include implementing DFT features, generating test patterns, and diagnosing coverage or test failures.

• Design and implement scan insertion flows and compression scan structures.
• Implement and verify memory built-in self-test (MBIST) and logic BIST (LBIST) where applicable.
• Generate ATPG patterns to meet target fault coverage and quality metrics.
• Analyze and debug ATPG failures and simulation mis-compares; determine root causes and corrective actions.
• Verify ATPG testbenches and support equivalency/timing checks related to DFT insertion.
• Work with synthesis and verification teams; support timing analysis and equivalency checks as needed.
• Coordinate with cross-functional stakeholders (Architecture, Design, Verification, customers) to integrate DFT into project flows.
• Deliver DFT tasks independently and mentor less experienced engineers when required.

Requirements

Must-have skills and relevant preferences.

• 3–12 years of professional SoC/ASIC digital design experience with a focus on DFT.
• Intimate knowledge of DFT insertion flows and scan chain insertion using synthesis or other tools.
• Experience with compression scan insertion and other scan technologies.
• Expertise in ATPG and experience generating patterns to meet coverage goals and quality metrics.
• Experience with MBIST and debug/analysis of test failures to improve fault coverage.
• Experience verifying ATPG testbenches and debugging simulation mis-compares.
• Working knowledge of JTAG (1149.1/1149.6), IEEE 1500, and IEEE 1687.
• Strong problem-solving skills; disciplined, methodical approach; ability to work in fast-paced projects.
• Ability to work collaboratively across cross-functional teams and to complete DFT tasks independently.
• Preference: Prior experience with Cadence tools and flows.
• Preference: US citizenship preferred.

Education Requirements

Not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.