DFT Design Engineer
Cadence Design SystemsJob Title
DFT Design Engineer
Role Summary
Work as a SoC/ASIC digital engineer focused on Design for Test (DFT) to improve silicon testability and achieve target test coverage. The role involves scan chain insertion, compression scan technologies, MBIST development, ATPG pattern generation, failure analysis, and cross-functional collaboration.
Position is within Cadence's digital design organization and requires US citizenship.
Experience Level
Mid-level — 2–10 years of professional experience in SoC/ASIC digital design with a focus on DFT.
Responsibilities
Drive DFT implementation and verification activities across the ASIC/SoC lifecycle to meet test coverage and quality metrics.
- Plan and execute scan chain insertion using synthesis or EDA tools.
- Implement compression scan insertion and related scan technologies.
- Design, implement, and verify memory BIST (MBIST) solutions.
- Generate ATPG patterns to meet fault coverage goals and follow systematic quality metrics.
- Debug and analyze test and simulation failures to improve fault coverage.
- Verify ATPG testbenches and root-cause debug of simulation mis-compares.
- Work with JTAG (1149.1/1149.6), IEEE1500, and IEEE1687 infrastructures.
- Collaborate with architecture, design, and internal/external customers to deliver DFT features.
- Execute DFT tasks independently and meet project timelines.
Requirements
Required technical skills, experience, and eligibility for the role.
- 2–10 years professional experience in SoC/ASIC digital design with a focus on DFT.
- Proven experience with scan chain insertion flows.
- Experience with compression scan insertion and other scan technologies.
- Experience designing and verifying MBIST for memories.
- Expertise in ATPG and achieving design test coverage targets; familiarity with quality-metrics-driven ATPG.
- Ability to debug and analyze failures to improve fault coverage.
- Experience verifying ATPG testbenches and debugging simulation mis-compares.
- Working knowledge of JTAG 1149.1/1149.6, IEEE1500, and IEEE1687.
- Ability to work collaboratively across cross-functional teams and independently execute tasks.
- US citizenship required.
Nice-to-have:
- Hands-on experience with synthesis, verification, and debugging Verilog testbenches.
- Knowledge of timing analysis and equivalency checks.
- Prior experience with Cadence tools and flows.
Education Requirements
Not specified.
About the Company
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
