DFT Design Engineer

Job Title

DFT Design Engineer

Role Summary

Join Intel's Wireless Connectivity Group (WCS) Silicon team to design and validate Design-for-Test (DFT) features for WiFi/BT IP blocks and SoCs. The role focuses on ensuring testability and manufacturability, enabling rapid bring-up and high-volume production.

The position requires collaboration with architecture, verification, post-silicon, and manufacturing teams to deliver robust DFT solutions and production test content.

Experience Level

Mid-level — typically requires around 4+ years of experience in DFT engineering.

Responsibilities

Key responsibilities include design, integration, verification, and production support for DFT features.

• Develop RTL and structural code for DFT features such as SCAN, MBIST, and BSCAN.
• Provide DFT timing-closure support and deliver test content for manufacturing (ATE).
• Define and influence architecture and microarchitecture for blocks, subsystems, and SoCs with DFT considerations.
• Apply tools and strategies to generate RTL and structural DFT integration code and test vectors.
• Optimize designs for power, performance, area, timing, test coverage, DPM, and test time/vector memory.
• Review and drive verification plans to ensure DFT features meet specifications.
• Debug failing RTL tests and support silicon bring-up and post-silicon debug activities.
• Integrate DFT blocks into functional IP and SoC and support downstream customers for quality integration.
• Develop and document high-volume manufacturing content and lessons learned with manufacturing teams.

Requirements

Must-have technical skills and practical experience; preferred skills listed separately.

• Must-have: 4+ years of hands-on DFT engineering experience.
• Must-have: Strong knowledge and practical experience with Scan ATPG.
• Must-have: Hands-on RTL design experience and proficiency with SystemVerilog and digital design fundamentals.
• Must-have: Experience with EDA tools and flows, including linting and timing/clock exception handling (MCO, timing closure).
• Must-have: Experience developing test automation, driving high test coverage, and preparing production test content for ATE.
• Must-have: Experience integrating and validating DFT features in IP and SoC environments and supporting manufacturing/post-silicon debug.
• Nice-to-have: Demonstrated problem-solving skills and experience improving test time, coverage, or vector memory efficiency.
• Nice-to-have: Strong communication and cross-functional collaboration skills.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (as stated in the posting).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.