DFT Design Engineer

Job Title

DFT Design Engineer

Role Summary

Own design-for-test strategy and execution for complex IP blocks, from architecture through sign-off. Work closely with design, verification, and physical implementation teams to ensure test readiness and meet coverage and manufacturing constraints.

Experience Level

Mid-level — typically requires 5+ years of hands-on DFT implementation experience.

Responsibilities

Primary responsibilities include:

• Execute block- and top-level ATPG, run DRC analysis, and optimize coverage to meet product and test-time targets.
• Perform timing-aware and non-timing pattern simulations and debug failures to root cause in the netlist or tool setup.
• Design and implement DFT architectures: scan insertion strategies, compression schemes, and BIST integration where required.
• Collaborate with design, verification, and physical design teams to resolve DFT issues and ensure test readiness through the flow.
• Own DFT sign-off activities and deliverables for assigned projects, acting as the DFT point of contact through tapeout.
• Define and execute DFT strategies aligned with schedules, coverage requirements, and manufacturing test constraints.
• Independently debug complex DFT simulation and netlist issues, resolve coverage gaps, DRC violations, and pattern failures.

Requirements

Must-have skills and experience; concise list of practical requirements and one noted preference.

• 5+ years of hands-on DFT implementation experience (scan insertion, ATPG, pattern validation).
• Proficiency with industry-standard DFT tools such as Synopsys TetraMAX, DFT Compiler, or equivalent.
• Demonstrated ability to debug complex DFT simulation failures, DRC violations, and coverage issues independently.
• Solid understanding of the VLSI design flow, including RTL, synthesis, and physical design interactions with DFT.
• Experience executing DFT sign-off for block-level or top-level designs in a production environment.
• Nice-to-have: experience with memory BIST, logic BIST, or advanced compression techniques.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.