Device Engineering Intern, ULP CMOS (Summer 2026)

Job Title

Device Engineering Intern, ULP CMOS (Summer 2026)

Role Summary

Work within the technology development organization on Ultra Low Power (ULP) CMOS device engineering to design, execute, and analyze experiments that optimize transistor technologies for product lines such as Smart Model Device, Automotive, IoT, and Aerospace & Defense.

The role involves test chip layout, device characterization, automation of device analysis, and collaboration with cross-functional technology and product teams to meet device, manufacturability, and reliability targets.

Experience Level

Entry-level intern. Targeted at students currently enrolled in a Bachelor's program (sophomore or above) pursuing a relevant technical degree.

Responsibilities

Primary responsibilities include:

• Design layout for device test chips.
• Execute inline and bench electrical tests and analyze results.
• Characterize device performance and variability; support test-chip experiments.
• Develop and automate device analysis workflows to improve standardization and efficiency.
• Work with technology development teams and product/market groups to define requirements and parametric goals.
• Monitor cost, variability, and reliability considerations to support manufacturability.
• Follow Environmental, Health, Safety & Security (EHS) requirements in all activities.

Requirements

Must-have and preferred qualifications for successful candidates.

• Must-have: English fluency (written and verbal).
• Must-have: Availability to work full-time (at least 40 hours/week) for the duration of the internship.
• Must-have: Ability to perform laboratory and bench test activities while following EHS protocols.

Preferred / Nice-to-have:

• Prior related internship or co-op experience.
• Leadership experience in projects, competitions, or student organizations.
• Project management skills and ability to execute solutions in ambiguous environments.
• Strong written and verbal communication, planning, and organizational skills.
• Knowledge of CMOS fabrication processes and solid-state device physics.
• Understanding of submicron FET architectures and implications of device characteristics.

Education Requirements

Currently enrolled and actively pursuing a Bachelor’s degree in Electrical Engineering, Materials Science, Solid State Physics, or a closely related technical field from an accredited program; at least a sophomore standing at time of application. Must have at least a 3.0 overall GPA and be in good academic standing.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.