Design Verification Senior Staff Engineer

Job Title

Design Verification Senior Staff Engineer

Role Summary

Senior verification engineer responsible for end-to-end verification and signoff of PCIe and CXL subsystems within the Center of Excellence (Custom Compute and Storage BU). The role designs and implements UVM/SystemVerilog testbenches, drives coverage- and protocol-compliance closure, and collaborates with design, architecture, firmware, and validation teams.

Focus areas include PCIe Gen6/Gen7, CXL 3.0/4.0 protocols, subsystem- and system-level verification, performance validation, and automation to accelerate regression and coverage.

Experience Level

Senior — listed experience: 5–10 years in ASIC/SoC verification.

Responsibilities

Primary responsibilities include verification planning, testbench development, debugging, and coverage closure for high-speed interfaces.

• Own end-to-end verification of PCIe (Gen6/Gen7) and CXL (3.0/4.0) subsystems from test planning through coverage closure and signoff.
• Define and execute verification plans based on protocol specifications and micro-architecture requirements.
• Architect and develop scalable UVM/SystemVerilog testbenches; integrate and configure PCIe/CXL VIP.
• Validate CXL.io, CXL.cache, and CXL.mem protocols, including coherency and memory semantics across complex flows.
• Develop constrained-random and directed test suites and implement SystemVerilog Assertions (SVA) for protocol compliance.
• Debug complex failures (protocol violations, ordering issues, coherency bugs) using waveforms, logs, and protocol analyzers.
• Drive functional, code, and assertion coverage closure; identify gaps and implement targeted tests to meet signoff goals.
• Validate performance metrics (latency, throughput, QoS) under high-bandwidth and stress workloads.
• Develop automation (Python/Shell) for regression management, log triage, and coverage reporting.
• Collaborate with design, architecture, firmware and validation teams and mentor junior engineers.

Requirements

Clear distinction between required skills and preferred additions.

• Must-have: 5–10 years of ASIC/SoC verification experience; strong knowledge of PCIe and CXL protocols and architecture; expertise in SystemVerilog and UVM; experience debugging complex verification issues; familiarity with simulation, waveform debugging, and coverage tools; solid digital design fundamentals.
• Nice-to-have: Assertion-based verification (SVA); performance modeling and traffic generation; exposure to emulation platforms (e.g., Palladium, Veloce); scripting skills (Python/Perl/Shell); low-power verification (UPF); emulation/FPGA validation and post-silicon bring-up experience.
• Role may require eligibility to access export-controlled technology; candidates may be subject to export license review prior to employment.

Education Requirements

Bachelor's or master’s degree in Electrical Engineering, Computer Engineering, or a related technical field (as listed in the posting).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.