Design Verification Lead

Job Title

Design Verification Lead

Role Summary

Lead the verification strategy and team for Neurophos' silicon-photonics AI inference ASICs. Own verification methodology, testbench architecture, and integration of verification flows from module level through SoC and tapeout validation. Reports to the Director of Digital Design. Onsite in Austin, TX or Sunnyvale, CA.

Experience Level

Senior - 8 to 15 years of design verification experience, including leading verification on GPU-class or complex compute ASICs through tapeout.

Responsibilities

Primary responsibilities include:

• Define and own verification methodology and testbench architecture using UVM and SystemVerilog, incorporating AI-assisted flows where appropriate.
• Develop the verification plan across levels: module simulation, SoC integration, interface checks, top-level IO, and validation handoff.
• Specify, evaluate, and integrate third-party VIP into the environment; drive gate-level (SDF-annotated) simulation for tapeout closure.
• Extend FPGA-based verification harnesses to exercise modules with real software quickly and cost-effectively.
• Stand up and operate emulation environments, including cloud-hosted provisioning and execution.
• Use coverage feedback and AI tooling to generate and iterate testbenches and assertions to achieve coverage targets.
• Build and lead the verification team, and collaborate with system architecture, RTL, physical design, DFT, and validation teams.

Requirements

Must-have:

• 8–15 years of design verification experience; proven leadership of verification on a GPU-class or complex compute ASIC through tapeout.
• Deep expertise in UVM and SystemVerilog, including testbench architecture, formal verification, coverage analysis, and CI/CD for verification.
• Practical gate-level simulation experience and knowledge of its role and limitations in a tapeout schedule.
• Experience verifying chips with multiple independently developed blocks and analog components, including integrating analog models.
• Experience standing up verification environments end-to-end, including emulation and FPGA-based flows.

Nice-to-have:

• Hands-on emulation experience (e.g., Palladium or equivalent).
• Experience developing analog models (WREAL or equivalent) and FPGA prototyping.
• Familiarity with Cadence toolchain and AI tooling to accelerate testbench development and coverage closure.
• Exposure to silicon photonics or optical component verification.

Education Requirements

Not specified.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.