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Design Verification Intern, BS - Summer 2027

Marvell Technology
September 07, 2026
Internship
On-site
Santa Clara, California, United States
$30 - $59 USD hourly
Verification Jobs, Level - Entry or Early Career

Job Title

Design Verification Intern (BS) — Summer 2027

Role Summary

This internship supports Marvell's Design Verification teams working on pre-silicon verification, ASIC/SoC testbenches, and full-chip verification across networking, storage, and AI domains.

The intern will build and run simulation environments, develop automated verification tests, analyze coverage and results, and work cross-functionally with architects, designers, and software engineers to validate designs.

Experience Level

Entry-level internship for undergraduate students; intended for those completing a Bachelor's degree and expecting graduation between Fall 2027 and Summer 2028.

Responsibilities

Typical tasks for the internship:

  • Study chip/SoC architecture and design intent to develop verification objectives.
  • Create and maintain simulation environments and UVM testbenches that model real-world scenarios.
  • Implement automated tests and test sequences to exercise RTL at block/cluster/full-chip levels.
  • Run simulations with EDA tools, analyze results, and identify functional failures and regressions.
  • Analyze coverage and verification metrics; propose and implement improvements to test suites.
  • Perform RTL integration and bring-up activities and debug hardware/software interactions.
  • Document findings, file clear bug reports, and communicate results to cross-functional teams.

Requirements

Core skills and experience expected from candidates.

  • Must-have: Proficiency in programming/scripting (Python, C, C++, Perl, or Java).
  • Must-have: Experience using industry EDA simulation tools (Synopsys, Cadence, or Mentor) to run simulations and debug testbenches.
  • Must-have: Hands-on experience with RTL integration and bring-up; ability to debug complex hardware/software interactions.
  • Must-have: Strong analytical, problem-solving, and written/verbal communication skills.
  • Nice-to-have: Familiarity with UVM, Verilog, VHDL, SoC/ASIC verification methodologies, and coverage analysis tools.

Education Requirements

Currently enrolled in a Bachelor’s degree program in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with expected graduation between Fall 2027 and Summer 2028. Relevant coursework includes computer architecture, digital logic/processor and memory systems, Verilog/VHDL, UVM, VLSI/IC design, and verification principles.


About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.

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Date Posted: 2026-09-06