Design Verification Infrastructure Sr. Staff Engineer

Job Title

Design Verification Infrastructure Sr. Staff Engineer

Role Summary

Join Marvell's Central CAD engineering group to build and operate a deterministic, Python-based design verification infrastructure used by ASIC DV teams. The role owns core framework components that ensure reproducible builds, runs, verdicts, and coverage while enabling an AI layer for triage and run selection.

Experience Level

Senior. Hiring guidance in the posting indicates typically 3–5 years of relevant professional experience with a Bachelor's, or 2–3 years with an advanced degree, or equivalent professional experience.

Responsibilities

Deliver and operate production-quality verification infrastructure components and integrations for DV teams:

• Design and own Python framework components: declarative build graph importer, run-record store, coverage merge, and verdict logic.
• Develop simulator backend abstractions (command generation and capability modeling) for Cadence Xcelium and Synopsys VCS.
• Create compact, self-contained failure bundles (waveforms, logs, run metadata) for downstream debugging and automation.
• Integrate with compute-grid job submission, results dashboard, CI for gate-blocking paths, and agent endpoints.
• Support an AI triage layer by authoring reusable agent prompts/skills and evaluation harnesses while enforcing deterministic guardrails.
• Package, deploy, monitor, and troubleshoot the flow across verification teams and sites.
• Write documentation and reusable procedures to enable adoption by other teams.

Requirements

Must-have technical skills and behaviors, followed by concise nice-to-have items.

• Must-have: Strong, idiomatic Python with emphasis on clean, testable code and command-line tooling.
• Comfortable with Linux, command-line operations, and Git.
• Solid data-structures fundamentals, including graphs/DAGs (the build model is a dependency graph).
• Working knowledge of CI/CD and experience delivering components end-to-end.
• Self-directed contributor with clear written communication for distributed teams.

Nice-to-have:

• Hardware-verification fundamentals and exposure to SystemVerilog/UVM.
• Hands-on experience with EDA simulators (Cadence Xcelium and/or Synopsys VCS).
• Familiarity with coverage collection, merge, and closure workflows.
• Experience using AI coding agents and integrating agent/tool endpoints (MCP) or compute-grid schedulers (LSF, SLURM, SGE).

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field with ~3–5 years of relevant experience; or a Master's/PhD in Computer Science, Electrical Engineering, or related field with ~2–3 years of experience. The posting also allows equivalent professional experience in lieu of a formal degree.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.