Design Verification Infrastructure Sr. Staff Engineer

Job Title

Design Verification Infrastructure Sr. Staff Engineer

Role Summary

Build and operate the Python-based core of an AI-integrated verification design environment within Marvell Central CAD Engineering. The role owns deterministic framework components (build graph, run-record store, coverage merge, verdict logic) and integrates an AI layer for triage and test selection while ensuring reproducibility and guardrails.

Experience Level

Senior level (title: Sr. Staff). Note: the job text also includes a line mentioning new graduates up to ~5 years of experience, which appears inconsistent with the senior title.

Responsibilities

Deliver, deploy, and operate core verification-infrastructure components and integrations used daily by DV engineers.

• Design and implement core Python framework components: declarative build graph importer, run-record store, coverage merge, and verdict logic.
• Develop a simulator backend abstraction that encapsulates command generation and capability modeling for tools such as Cadence Xcelium and Synopsys VCS.
• Assemble compact failure bundles (waveforms, logs, run-record metadata, testbench config, source pointers) for downstream debugging and agents.
• Integrate with compute-grid job submission, results dashboards, CI for gate-blocking paths, and agent-facing endpoints.
• Support an AI layer by authoring reusable agent skills and prompts, building evaluation harnesses, and enforcing deterministic guardrails.
• Package, deploy, monitor, and troubleshoot the flow across sites; write documentation and adoption procedures.

Requirements

Key skills and attributes required to perform the role.

• Must-have: Strong, idiomatic Python with emphasis on testable code and CLI tooling.
• Must-have: Comfortable on Linux, proficient with Git and command-line workflows.
• Must-have: Solid data-structures fundamentals, including graphs/DAGs (build model is a dependency graph).
• Must-have: Working knowledge of CI/CD and the ability to deliver a component end-to-end with minimal supervision.
• Must-have: Clear written communication and ability to collaborate across distributed teams.
• Nice-to-have: Hardware-verification fundamentals and exposure to SystemVerilog/UVM.
• Nice-to-have: Hands-on experience with EDA simulators (Cadence Xcelium, Synopsys VCS).
• Nice-to-have: Experience with coverage collection, merge, and closure.
• Nice-to-have: Familiarity with AI coding agents and evaluating their outputs.
• Nice-to-have: Exposure to agent/tool integration (MCP) and compute-grid schedulers (LSF, SLURM, SGE).

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, or Computer Science is stated. The posting also notes consideration of new graduates (up to ~5 years) with substantial internship or project experience. No additional certification requirements are specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.