Design Verification Engineer to Staff Engineer (Unit Level Test)

Job Title

Design Verification Engineer to Staff Engineer (Unit Level Test)

Role Summary

Work on unit-level verification of memory subsystems and interconnects for SiFive RISC-V products. Collaborate with CPU designers, compiler, performance, and system verification teams to generate automated, coverage-driven tests and establish a scalable, reusable constrained-random UVM testbench.

Experience Level

Senior — title includes "Staff". The posting requests at least 3+ years of relevant verification experience.

Responsibilities

Primary responsibilities focus on verification planning, test infrastructure, and coverage closure for memory and interconnect features.

• Collaborate with design and system teams to review specs, define verification requirements, and produce test plans.
• Generate automated, coverage-driven tests (constrained-random) to meet cross-team verification needs.
• Develop checkers and assertions for memory subsystem and interconnect verification.
• Implement and maintain testbenches, test suites and tools (UVM, C/C++, or other languages as needed).
• Develop and maintain in-house Verification IP (VIP) for memory and interconnect testing.
• Write and analyze functional coverage and close coverage holes through targeted tests and failure analysis.

Requirements

Must-have skills and experience required to perform the role; a few items noted as nice-to-have.

• Must-have: 3+ years recent experience with verification tools and methodologies (SystemVerilog/UVM, Verilog, Verdi/DVE, Makefiles, scripting languages).
• Must-have: Strong familiarity with verification flow: test-plan generation, test generation, failure analysis, coverage analysis and closure.
• Must-have: Experience developing checkers, assertions, testbenches, and verification IP; ability to build reusable, scalable constrained-random environments.
• Must-have: Proven troubleshooting skills and strong analytical capability.
• Must-have: Good interpersonal and communication skills to interact with cross-functional teams.
• Nice-to-have: Familiarity with AMBA protocols.
• Nice-to-have: Existing understanding of processor and SoC architecture (or demonstrated ability and motivation to learn quickly).

Education Requirements

Not specified.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.