Design Verification Engineer, Senior Staff
QualcommJob Title
Design Verification Engineer, Senior Staff
Role Summary
Lead verification architecture and execution for DSP products, SerDes integration, full-chip SoC verification, and ATE functional test validation. Collaborate with design, DFT, firmware, silicon validation, product engineering and ATE teams to move test content from simulation to silicon and production.
Experience Level
Senior - typically requires 10+ years of ASIC/SoC design verification experience.
Responsibilities
Primary responsibilities include verification planning, environment development, and driving verification closure across pre- and post-silicon phases.
- Architect, develop, and maintain scalable SystemVerilog/UVM verification environments for DSP, SerDes, SoC interconnects, and full-chip integration.
- Lead verification of DSP functionality, datapaths, control logic, configuration, performance modes, and system-level integration.
- Verify SerDes integration: calibration, CDR/PLL control, equalization, lane configuration, deskew, loopback, and interface behavior.
- Plan and own SoC-level verification for reset/boot flows, clocking, power states, interrupts, CDC/RDC, registers, and high-speed datapaths.
- Develop ATE functional test content, support simulation-to-silicon transition, and drive production vector signoff.
- Drive metric-based verification closure across functional coverage, code coverage, assertions, and regression results.
- Debug complex multi-clock, multi-power-domain RTL, testbench, firmware, and system integration issues.
- Provide technical leadership, mentor engineers, and improve regression efficiency, automation, and debug methodologies.
Requirements
Must-have skills and experience for successful performance in this role.
- 10+ years of ASIC/SoC design verification experience.
- Strong hands-on expertise with SystemVerilog and UVM (agents, sequences, monitors, scoreboards, checkers, coverage).
- Experience verifying DSP products, complex SoC subsystems, full-chip integration, and high-speed interfaces.
- Deep understanding of SerDes digital integration, PMA/PCS interfaces, calibration, training, equalization, clocking, and lane management.
- Experience developing or validating functional test content for ATE, production test, silicon bring-up, or post-silicon validation.
- Proficiency with simulation, debug, and coverage tools (VCS/Verdi, Xcelium, Questa).
- Strong scripting and automation skills (Python, Perl, Bash, Make, or similar).
- Proven ability to lead technical execution across cross-functional and geographically distributed teams.
Preferred:
- Experience with DSP architectures, signal-processing datapaths, or high-throughput data-processing blocks.
- Familiarity with high-speed protocols such as PCIe, CXL, Ethernet, or custom multi-gigabit PHYs.
- Experience correlating pre-silicon simulation with post-silicon lab validation or ATE fallout.
- Familiarity with UPF-based power-aware simulation and formal/property verification (SVA, JasperGold).
- Experience improving regression infrastructure, failure triage, and automated debug workflows.
Education Requirements
Bachelor's degree in Science, Engineering, or related field with 6+ years' related experience; OR Master's degree with 5+ years; OR PhD with 4+ years. The posting allows equivalent practical experience in lieu of degree-level requirements.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
