Design Verification Engineer - PCIE

Responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM. Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology. You are expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Experience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog Experience in developing and working in functional coverage based constrained random verification environments Experience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug