Design Verification Engineer - Memory Subsystem

Job Title

Design Verification Engineer - Memory Subsystem

Role Summary

Join the memory-subsystem verification team to define and execute verification strategies for memory controllers, PHY interfaces, and related high-performance memory components (DDR/LPDDR/HBM and custom interfaces). You will own verification plans, build UVM-based testbenches, write assertions, run regressions, debug failures, and drive coverage closure.

Experience Level

Mid-level - 3–10 years of experience in ASIC/SoC/IP/subsystem design verification or equivalent industry experience.

Responsibilities

Key responsibilities include planning and delivering verification for complex RTL and memory subsystems.

• Develop verification strategies, test plans, and coverage plans for memory-subsystem RTL.
• Design, enhance, and maintain reusable SystemVerilog/UVM verification environments and formal checks.
• Implement UVM components: sequences, drivers, monitors, scoreboards, agents, environments, and reference models.
• Create and run constrained-random, directed, error-injection, and corner-case tests.
• Write and maintain SystemVerilog Assertions for protocol, timing, and functional checks.
• Verify memory-controller, PHY-interface, and subsystem functionality across operating modes.
• Analyze simulation failures using waveforms, logs, and transaction databases; perform root-cause analysis and track fixes.
• Review RTL, microarchitecture, and interface specifications for verifiability and correctness.
• Execute regressions, triage failures, report verification status, and drive functional/code/coverage closure.
• Collaborate with architecture, RTL design, physical design, firmware, modeling, and system validation teams.

Requirements

Must-have technical skills and experience for immediate contribution.

• 3–10 years of ASIC/SoC/IP or subsystem verification experience.
• Hands-on experience with Verilog, SystemVerilog, UVM, and SystemVerilog Assertions (SVA).
• Proven experience developing and debugging reusable UVM-based verification environments and components.
• Experience with constrained-random and coverage-driven verification methodologies.
• Strong debugging skills with simulation-based verification, waveform analysis, and regression workflows.
• Solid understanding of digital design fundamentals: clocking, reset, synchronous/asynchronous logic, and multi-clock-domain designs.
• Strong analytical, problem-solving, communication, and cross-team collaboration skills.

Nice-to-have:

• Experience verifying LPDDR/DDR/HBM, DDR PHY, or custom memory interfaces and familiarity with JEDEC specs.
• Knowledge of AXI/APB/AHB/DFI or similar standard interfaces and memory models.
• Experience with formal or assertion-based verification and power-aware simulation (UPF).
• Experience with performance verification (bandwidth, latency, QoS) and hardware/software co-verification.

Education Requirements

Bachelor's, Master’s, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Science, Engineering, or a related technical field. Acceptable alternatives include equivalent practical experience as specified in the posting (e.g., Bachelor's + 2+ years, Master's + 1+ year, or PhD).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.