Design Verification Engineer - Memory Controller IP
ArmJob Title
Design Verification Engineer - Memory Controller IP
Role Summary
Join the Memory Controller IP verification team to develop verification strategies and SystemVerilog/UVM environments that validate functionality, performance, and protocol behavior for next-generation memory technologies. Work closely with RTL designers, architects, and verification colleagues to investigate issues and drive verification closure for assigned features.
Experience Level
Mid-level. Prior experience verifying ASIC or SoC designs using SystemVerilog/UVM is expected; no specific years of experience were listed.
Responsibilities
Deliver verification environments, tests, and analysis to achieve feature sign-off for Memory Controller IP.
- Develop and maintain SystemVerilog/UVM verification environments, testbenches, and scoreboards.
- Create verification plans, test scenarios, assertions, and functional coverage models from architectural specifications.
- Implement constrained-random and directed tests covering LPDDR and DDR memory technologies.
- Analyze regressions, coverage reports, simulation waveforms, and logs to isolate RTL, testbench, and protocol issues.
- Collaborate with RTL designers, architects, and verification teams to clarify behavior and resolve issues.
- Improve verification efficiency through scripting, automation, and methodology enhancements.
- Take ownership of assigned features and deliver verification milestones to agreed schedules.
Requirements
Core qualifications required for successful performance in this role.
- Practical experience verifying ASIC/SoC designs using SystemVerilog and UVM, including constrained-random testing, assertions, scoreboards, and functional coverage.
- Ability to develop verification plans and translate architectural specifications into tests, coverage, and verification environments.
- Understanding of memory controller architecture and memory protocol concepts (LPDDR or DDR technologies).
- Ability to debug RTL, testbench, and protocol issues using simulation tools, waveforms, and logs, and to communicate findings clearly with cross-functional teams.
Nice-to-have:
- Experience with LPDDR5/LPDDR6, DDR5/DDR6 or other memory technologies.
- Knowledge of DFI interfaces (DFI 4.x or 5.x) and AMBA protocols such as AXI, ACE, or CHI.
- Familiarity with simulation and debug tools (e.g., Synopsys VCS, Siemens Questa).
- Experience improving verification workflows through scripting, automation, or methodology development.
Education Requirements
Not specified.
About the Company
Company: Arm
Headquarters: Cambridge, United Kingdom
ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.
