Design Verification Engineer - Internal IP

Job Title

Design Verification Engineer - Internal IP

Role Summary

Join the Internal IP DV team to validate and qualify custom on-chip IP (systolic arrays, DMA engines, NoCs, memory subsystems) for silicon. The role focuses on building and running verification environments, finding and debugging functional and performance issues, and enabling production-quality IP.

You will work closely with architects, RTL designers, and SW/FW/emulation teams to deliver robust, high-throughput IP ready for tape-out and system bring-up.

Experience Level

Mid-level (Level - Mid-Career). Candidates typically have several years of design verification experience; 3–7 years is a common range for this role.

Responsibilities

The primary responsibilities center on verification planning, environment development, and cross-team validation.

• Develop and maintain UVM/SystemVerilog testbenches for compute arrays, DMA engines, NoCs, and memory subsystems.
• Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
• Debug complex datapath and protocol issues in RTL and testbench environments.
• Collaborate with architects and RTL designers to validate design intent and identify design-for-test improvements.
• Partner with software, firmware, and emulation teams to ensure end-to-end bring-up and debug coverage.
• Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

Requirements

Concise list of must-have and nice-to-have skills and experience.

• Must-have:
  • Proficiency with UVM and SystemVerilog.
  • Strong debugging and problem-solving skills for complex digital designs and testbenches.
  • Solid knowledge of computer architecture and digital design fundamentals.
  • Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
  • Effective collaboration and communication with RTL, architecture, and SW/FW teams.
• Nice-to-have:
  • Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
  • Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
  • Scripting skills (Python / Perl / TCL) for automation, debugging, and regression flows.
  • Experience with emulation or hardware bring-up workflows.

Education Requirements

Not specified.

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.