Design Verification Engineer II – CPU Subsystem

Job Title

Design Verification Engineer II – CPU Subsystem

Role Summary

Individual-contributor role responsible for owning verification planning and execution for CPU subsystem functionality in high-performance core development. You will define verification strategy for assigned subsystem areas, implement scalable test environments, and drive closure to signoff quality.

This role partners with architecture, RTL, performance, compiler, system verification, and software teams. Employment offers are contingent on background checks and applicable export-control approvals.

Experience Level

Mid-level (Engineer II). The posting targets engineers with approximately 5–8 years of relevant IP/component or CPU/core functional verification experience.

Responsibilities

Key responsibilities include planning, implementing, and executing verification activities from block level through subsystem integration and signoff.

• Own verification planning and execution for one or more CPU subsystem areas (block-level to subsystem signoff).
• Review specifications and microarchitecture to identify ambiguities and improve design debuggability.
• Develop and maintain scalable verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Define and run directed and constrained-random tests targeting pipeline interactions, load/store ordering, hazards, memory consistency, and related behaviors.
• Perform failure analysis and root-cause debug across specification, RTL, tests, and infrastructure.
• Write and analyze functional coverage and close coverage gaps to achieve verification completeness.
• Contribute reusable verification methodology, automation, and infrastructure improvements.
• Collaborate cross-functionally with architecture, design, compiler, performance, and system teams to close verification gaps.

Requirements

Must-have skills and experience required to perform the role; preferred items follow.

• Must-have: Strong hands-on experience with SystemVerilog and UVM-based verification.
• Must-have: Direct experience with CPU/core verification and solid understanding of computer architecture and CPU microarchitecture.
• Must-have: Experience in one or more CPU subsystem areas such as Frontend, Midcore, Load-Store Unit, memory ordering and consistency, or hardware prefetch verification.
• Must-have: Strong knowledge of verification flow and methodology: test planning, stimulus generation, failure analysis, coverage analysis, and closure.
• Must-have: Strong debug skills and ability to translate architectural intent into verification strategy and execution.
• Nice-to-have: Experience with out-of-order core verification.
• Nice-to-have: Experience using formal verification, emulation, or performance-oriented verification for high-risk or performance-sensitive problems.
• Nice-to-have: Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation; experience with object-oriented programming principles.
• Nice-to-have: Experience mentoring engineers and influencing verification methodology beyond the immediate block or feature area.
• Nice-to-have: Strong interpersonal skills and ability to influence across disciplines.

Education Requirements

Bachelor's or Master's degree (BS/MS) in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.