Design Verification Engineer II — CPU Subsystem

Job Title

Design Verification Engineer II — CPU Subsystem

Role Summary

Individual-contributor role owning verification of CPU subsystem functionality for high-performance cores. Work spans block-level verification through subsystem integration and signoff within an Out-of-Order core team.

Collaborate with architecture, RTL, performance, compiler, system verification, and software teams to capture design intent, identify risks early, and achieve signoff-quality verification.

Experience Level

Mid-level (Engineer II). The posting indicates 5–8 years of relevant IP/component or core verification experience as guidance.

Responsibilities

Primary responsibilities include planning and executing verification activities for CPU subsystems and improving verification methodology.

• Own verification planning and execution for one or more CPU subsystem areas from block-level through subsystem integration and signoff.
• Review specifications and microarchitecture to identify ambiguities and improve design debuggability.
• Develop and maintain verification environments: checkers, scoreboards, assertions, stimulus, and coverage models.
• Define and execute directed and constrained-random tests targeting pipeline interactions, load/store ordering, hazards, memory consistency, and related behaviors.
• Drive failure analysis and root-cause debug across spec, RTL, tests, and infrastructure.
• Write and analyze functional coverage and close coverage holes to reach verification completeness.
• Contribute reusable methodology, automation, and infrastructure improvements across CPU generations.
• Partner across design, architecture, compiler, performance, and system teams to close verification gaps.

Requirements

Must-have technical skills and qualifications for successful execution of the role.

• Must-have: Strong hands-on experience with SystemVerilog and UVM-based verification.
• Must-have: Direct CPU/core verification experience and solid understanding of computer architecture and microarchitecture.
• Must-have: Experience in one or more CPU subsystem areas such as Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
• Must-have: Strong verification flow knowledge: test planning, stimulus generation, failure analysis, coverage analysis, and closure.
• Must-have: Strong debug skills and the ability to translate architectural intent into verification strategy.
• Nice-to-have: Experience with out-of-order core verification.
• Nice-to-have: Experience with formal methods, emulation, or performance-focused verification for high-risk problems.
• Nice-to-have: Familiarity with Python, C/C++, or other scripting/programming languages used for DV infrastructure and automation.
• Nice-to-have: Experience mentoring engineers and influencing verification methodology beyond a single block.
• Role requires successful background and reference checks, verification of right to work in the United States, and export-control clearance as applicable.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (BS/MS in EE, CE, or CS cited).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.