Design Verification Engineer

Job Title

Design Verification Engineer

Role Summary

Perform functional verification of FPGA/ASIC designs by developing test plans, building constrained-random SystemVerilog/UVM testbenches, and validating design specifications. Join the verification team based in Manila supporting R&D for programmable logic products.

Experience Level

Mid-level — approximately 3+ years of relevant design verification experience.

Responsibilities

Primary responsibilities include:

• Develop test plans from design specifications.
• Design and implement constrained-random SystemVerilog/UVM testbenches and verification metrics.
• Code, run, and debug verification tests; triage issues and drive them to closure.
• Analyze and collate test results; produce verification reports and documentation.

Requirements

Must-have skills and conditions:

• Hands-on experience with SystemVerilog and UVM.
• Strong debugging and analysis skills; familiarity with HDL and FPGA concepts is preferred.
• Experience with industry-standard digital simulators and debugging tools.
• Good communication, collaboration, and documentation skills.
• Ability to pass background checks and provide proof of right to work in the Philippines.

Nice-to-have:

• Experience with Python, make, C, or C++.
• Experience with Siemens EDA tools.
• Familiarity with Perforce, Git, Jenkins, or generative AI tools.
• Domain experience in cryptography, security, AMBA protocols, SPI, I2C/I3C.

Education Requirements

Bachelor's (BS) or Master's (MS) degree in Computer, Electronics, or Electrical Engineering. The posting specifies a minimum of 3 years of relevant design verification experience.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.