Design Verification Engineer - Compute

Job Title

Design Verification Engineer - Compute

Role Summary

Join the Hardware verification team responsible for verification methodology and execution for compute subsystems and full-chip validation. The role focuses on building scalable verification flows, creating testbenches and tests, and driving verification to coverage closure for tapeout milestones.

Experience Level

Mid-level (Mid-Career) - minimum ~5 years of silicon design verification experience.

Responsibilities

Core responsibilities include planning and executing verification activities from subsystem to chip level and ensuring sign-off readiness.

• Develop and scale verification methodology across blocks, subsystems, and full-chip/system validation.
• Own verification execution for assigned subsystems and chip-level scopes; implement testbenches and verification infrastructure.
• Create tests and drivers to achieve structural and functional coverage closure and support post-silicon validation.
• Plan and drive verification reviews and sign-off activities toward design freeze and tapeout milestones.
• Collaborate with architecture, design, and bring-up teams for verification closure and silicon debug.

Requirements

Must-have skills and constraints for the role.

• At least 5 years of silicon design-verification experience with end-to-end, concept-to-silicon tapeout ownership.
• Production experience with SystemVerilog and UVM, assertion-based verification (ABV); familiarity with both formal and simulation-based verification.
• Proficiency with scripting and programming for verification: Python and C/C++ (used for verification and silicon modeling).
• Experience creating portable tests/drivers applicable to silicon validation and post-silicon debug.
• Strong understanding of silicon micro-architecture and design concepts for high-performance compute (CPUs, GPUs, accelerators), memory management, and related features.
• Ability to plan and execute verification sign-off activities toward tapeout and production silicon.
• Must be authorized to work in the United States and able to work from the Mountain View office Tuesdays–Thursdays.
• Role requires compliance with U.S. export control restrictions; employment contingent on ability to perform duties without an export license when required.

Nice-to-have:

• Numerics knowledge (floating-point/fixed-point arithmetic, rounding, precision).
• Experience with accelerators, DMA engines, or systolic-array designs.
• Experience with Rust, functional languages (Haskell), or functionally-rooted HDLs (Bluespec).
• Familiarity with emulation, prototyping platforms, silicon bring-up, and hardware debug.

Education Requirements

Not specified.

About the Company

Company: MatX

Headquarters: Mountain View, California, USA

MatX specializes in creating faster chips for large language models (LLMs), focusing on innovative hardware and software solutions. The company fosters a collaborative and supportive work environment, welcoming candidates of all experience levels. Their approach prioritizes deep understanding and consideration of novel methods to drive efficiency and performance in their projects, particularly in silicon design and related engineering roles.