Design Verification Engineer
Join the Design Verification team to develop and verify high-speed SerDes and PHY blocks used for PCIe, Ethernet and other industry-standard interfaces. The role focuses on building SystemVerilog/UVM verification environments, creating testbenches and coverage, and debugging RTL and verification infrastructure.
This is an early-career position working with experienced engineers on silicon that ships to production, with opportunity to learn and take ownership.
Entry-level / Early-career — 0–5 years of relevant experience (including internships or academic projects).
Primary responsibilities include verification of SerDes and PHY blocks at block and top level.
Must-have technical skills and experience:
Nice-to-have:
BSc in Electrical Engineering, Computer Engineering or equivalent; equivalent practical experience is accepted.
Company: Altera
Headquarters: Bengaluru, Karnataka, India
Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.
