Staff Design Verification Engineer

Job Title

Staff Design Verification Engineer

Role Summary

Lead verification efforts for power-management SoC blocks and subsystems, owning verification plans, environments, and closure criteria. Work within the verification team to drive block-to-chip verification and support quality sign-off for production silicon.

The role is technical and hands-on: architect verification environments, integrate VIPs, run gate-level flows, debug failures, and mentor junior engineers.

Experience Level

Senior. Overall 7–8+ years of industry experience with at least ~2 years using verification methodologies such as UVM.

Responsibilities

Primary responsibilities include planning, implementing, and delivering verification for complex SoC designs.

• Define verification plans, methodologies, and coverage strategies for complex SoC designs.
• Architect and implement verification environments and extend existing frameworks.
• Drive block-level, subsystem-level, and full-chip verification and closure activities.
• Develop agents, sequences, drivers, monitors, scoreboards, and automation infrastructure.
• Integrate industry-standard VIPs and create custom transactors where needed.
• Lead end-to-end verification: gate-level simulations, regressions, coverage analysis, triage, and debug to achieve quality sign-off.
• Mentor and provide technical leadership to junior and mid-level verification engineers.

Requirements

Must-have technical skills and experience to perform the role.

• 7–8+ years overall verification experience (senior-level experience preferred).
• Experience with industry-standard simulators, revision-control systems, and regression frameworks.
• Hands-on experience developing and maintaining verification testbenches, test cases, and environments.
• Strong knowledge of verification methodologies (UVM), directed and constrained-random verification techniques.
• Experience with Verilog, SystemVerilog, and familiarity with C/C++ for test infrastructure.
• Scripting and automation skills: Python and Shell scripting.
• Understanding of SoC architecture, mixed-signal design implications, and integration-level issues.
• Strong debugging, logical thinking, and analytical skills; excellent communication.
• Gate-level simulation and coverage closure experience (coverage analysis and debug of regressions).

Education Requirements

Bachelor's degree in Electrical Engineering is specified, or equivalent practical experience. (No other degrees or certifications are listed.)

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.