Design Verification Engineer

Job Title

Design Verification Engineer

Role Summary

Responsible for developing and executing verification strategies for FPGA and SoC digital designs. Work with architecture, RTL design, physical design, firmware, and software teams to ensure functional correctness and verification completeness across the product lifecycle.

Role focuses on SystemVerilog/UVM-based verification, assertion-based verification, coverage-driven approaches, and verification infrastructure to support simulation, emulation, and silicon bring-up.

Experience Level

Mid-level — typical candidate has 4+ years of industry experience in digital design verification (see Requirements for specific experience expectations).

Responsibilities

Primary responsibilities include planning, implementing, and validating verification environments and tests for complex digital blocks and subsystems.

• Develop and execute block- and subsystem-level verification plans and test strategies.
• Create reusable SystemVerilog/UVM verification environments, agents, sequences, scoreboards, and checkers.
• Develop constrained-random and directed tests and maintain functional coverage models.
• Write and maintain SystemVerilog Assertions (SVA) to catch functional issues early.
• Debug simulation failures and RTL functional issues; collaborate with RTL designers and architects.
• Perform coverage analysis (functional, code, toggle, assertion) and drive coverage closure.
• Build and maintain verification infrastructure, automation, and regression environments.
• Participate in design and verification reviews, bug triage, and cross-team integration activities.
• Support emulation, FPGA prototyping, and post-silicon validation as needed for product bring-up.

Requirements

Must-have technical skills and experience.

• 4+ years verifying digital ASIC, FPGA, or SoC designs using SystemVerilog and UVM.
• 4+ years developing constrained-random and directed verification testbenches for complex digital designs.
• 3+ years writing and using SystemVerilog Assertions (SVA) and applying assertion-based methodologies.
• 3+ years using industry simulators (examples: Synopsys VCS, Cadence Xcelium, Siemens QuestaSim) and debugging RTL via waveform analysis and simulation tools.
• 3+ years developing UVM components (agents, drivers, monitors, scoreboards), sequences, and functional coverage models.
• 3+ years analyzing functional, code, and assertion coverage and working toward coverage closure.
• 2+ years scripting to automate verification workflows (Python, Perl, Tcl, Shell, or similar).
• 2+ years using revision control systems such as Git or Perforce.
• Experience verifying high-speed digital interfaces (examples: PCIe, Ethernet, DDR/LPDDR, HBM, AXI, CXL, USB).

Nice-to-have / preferred skills:

• Experience with formal verification tools and methodologies.
• Experience with hardware emulation, FPGA prototyping, or acceleration-based verification.
• Experience developing reusable verification IP (VIP) for complex products.
• Familiarity with low-power verification methodologies (UPF/CPF), lint/CDC/static verification tools, and post-silicon validation or silicon bring-up.
• Experience applying coverage-driven verification at large scale and verifying complex FPGA architectures or configurable hardware systems.

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. Preferred: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.